Searched refs:REGISTER_PLL_DIV (Results 1 – 2 of 2) sorted by relevance
1529 #define REGISTER_PLL_DIV(s, ...) _REGISTER(&bcm2835_register_pll_divider, \ macro1694 [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(1704 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(1714 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(1723 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV(1751 [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(1783 [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(1793 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(1803 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(1813 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV([all …]
1302 #define REGISTER_PLL_DIV(...) _REGISTER(&rp1_register_pll_divider, \ macro1398 static struct rp1_clk_desc pll_sys_sec_desc = REGISTER_PLL_DIV(1413 static struct rp1_clk_desc pll_video_sec_desc = REGISTER_PLL_DIV(1560 static struct rp1_clk_desc pll_audio_sec_desc = REGISTER_PLL_DIV(1575 static struct rp1_clk_desc pll_audio_tern_desc = REGISTER_PLL_DIV(