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Searched refs:PixelClockBackEnd (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_util_32.h259 double PixelClockBackEnd,
330 double PixelClockBackEnd,
H A Ddisplay_mode_vba_util_32.c1346 double PixelClockBackEnd, in dml32_CalculateOutputLink() argument
1379 PixelClockBackEnd, ForcedOutputLinkBPP, false, Output, OutputFormat, in dml32_CalculateOutputLink()
1406 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1415 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1428 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1438 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1451 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1459 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1474 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1485 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
[all …]
H A Ddisplay_mode_vba_32.c348 v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 12 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
352 v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 6 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
356 v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 3 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
370 mode_lib->vba.PixelClockBackEnd[k], mode_lib->vba.ip.dsc_delay_factor_wa); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2097 mode_lib->vba.PixelClockBackEnd[k], in dml32_ModeSupportAndSystemConfigurationFull()
2418 mode_lib->vba.PixelClockBackEnd[k], in dml32_ModeSupportAndSystemConfigurationFull()
2466 …if (mode_lib->vba.PixelClockBackEnd[k] / 12.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->v… in dml32_ModeSupportAndSystemConfigurationFull()
2470 …if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vb… in dml32_ModeSupportAndSystemConfigurationFull()
2473 …if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vb… in dml32_ModeSupportAndSystemConfigurationFull()
2528 mode_lib->vba.PixelClock[k], mode_lib->vba.PixelClockBackEnd[k], in dml32_ModeSupportAndSystemConfigurationFull()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_mode_vba_20.c1784 mode_lib->vba.PixelClockBackEnd[k] / 6 in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1791 mode_lib->vba.PixelClockBackEnd[k] / 3 in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1836 / mode_lib->vba.PixelClockBackEnd[k]; in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4057 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml20_ModeSupportAndSystemConfigurationFull()
4073 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20_ModeSupportAndSystemConfigurationFull()
4080 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20_ModeSupportAndSystemConfigurationFull()
4102 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20_ModeSupportAndSystemConfigurationFull()
4109 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20_ModeSupportAndSystemConfigurationFull()
4133 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20_ModeSupportAndSystemConfigurationFull()
4140 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20_ModeSupportAndSystemConfigurationFull()
[all …]
H A Ddisplay_mode_vba_20v2.c1820 mode_lib->vba.PixelClockBackEnd[k] / 6 in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1827 mode_lib->vba.PixelClockBackEnd[k] / 3 in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1872 / mode_lib->vba.PixelClockBackEnd[k]; in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4171 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml20v2_ModeSupportAndSystemConfigurationFull()
4188 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
4196 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
4219 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
4227 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
4252 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
4260 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_mode_vba_21.c1776 mode_lib->vba.PixelClockBackEnd[k] / 6 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1783 mode_lib->vba.PixelClockBackEnd[k] / 3 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1828 / mode_lib->vba.PixelClockBackEnd[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4265 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml21_ModeSupportAndSystemConfigurationFull()
4282 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml21_ModeSupportAndSystemConfigurationFull()
4290 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml21_ModeSupportAndSystemConfigurationFull()
4313 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml21_ModeSupportAndSystemConfigurationFull()
4321 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml21_ModeSupportAndSystemConfigurationFull()
4346 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml21_ModeSupportAndSystemConfigurationFull()
4354 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml21_ModeSupportAndSystemConfigurationFull()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_mode_vba_314.c2257 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 / v->DSCFormatFactor
2260 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 / v->DSCFormatFactor
2263 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 / v->DSCFormatFactor
2301 v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
4357 if (v->PixelClockBackEnd[k] > 3200) {
4358 v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0);
4359 } else if (v->PixelClockBackEnd[k] > 1360) {
4361 } else if (v->PixelClockBackEnd[k] > 680) {
4363 } else if (v->PixelClockBackEnd[k] > 340) {
4386 v->PixelClockBackEnd[k],
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_mode_vba_31.c2239 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 / v->DSCFormatFactor
2242 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 / v->DSCFormatFactor
2245 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 / v->DSCFormatFactor
2282 v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
4270 if (v->PixelClockBackEnd[k] > 3200) {
4271 v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0);
4272 } else if (v->PixelClockBackEnd[k] > 1360) {
4274 } else if (v->PixelClockBackEnd[k] > 680) {
4276 } else if (v->PixelClockBackEnd[k] > 340) {
4299 v->PixelClockBackEnd[k],
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddisplay_mode_core.c84 dml_float_t PixelClockBackEnd,
745 dml_float_t PixelClockBackEnd);
2699 display_cfg->output.PixelClockBackEnd[k] = display_cfg->timing.PixelClock[k]; in PixelClockAdjustmentForProgressiveToInterlaceUnit()
5351 dml_float_t PixelClockBackEnd, in CalculateOutputLink() argument
5384 …ncToValidBPP(dml_min(600, PHYCLKPerState) * 10, 3, HTotal, HActive, PixelClockBackEnd, ForcedOutpu… in CalculateOutputLink()
5410 …- Downspreading / 100) * 10000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutpu… in CalculateOutputLink()
5415 …- Downspreading / 100) * 10000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutpu… in CalculateOutputLink()
5423 …- Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutpu… in CalculateOutputLink()
5429 …- Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutpu… in CalculateOutputLink()
5437 …- Downspreading / 100) * 20000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutpu… in CalculateOutputLink()
[all …]
H A Ddml2_utils.c124 dml_output_array->PixelClockBackEnd[dst_index] = dml_output_array->PixelClockBackEnd[src_index]; in dml2_util_copy_dml_output()
H A Ddisplay_mode_core_structs.h626 dml_float_t PixelClockBackEnd[__DML_NUM_PLANES__]; member
H A Ddml2_translation_helper.c887 out->PixelClockBackEnd[location] = in->timing.pix_clk_100hz / 10000.00; in populate_dml_output_cfg_from_stream_state()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_mode_vba_30.c2015 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2018 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2021 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2056 v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3864 if (v->PixelClockBackEnd[k] > 3200) { in dml30_ModeSupportAndSystemConfigurationFull()
3865 v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0); in dml30_ModeSupportAndSystemConfigurationFull()
3866 } else if (v->PixelClockBackEnd[k] > 1360) { in dml30_ModeSupportAndSystemConfigurationFull()
3868 } else if (v->PixelClockBackEnd[k] > 680) { in dml30_ModeSupportAndSystemConfigurationFull()
3870 } else if (v->PixelClockBackEnd[k] > 340) { in dml30_ModeSupportAndSystemConfigurationFull()
3893 v->PixelClockBackEnd[k], in dml30_ModeSupportAndSystemConfigurationFull()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_dcn4_calcs.c429 …aceUnit(const struct dml2_display_cfg *display_cfg, bool ptoi_supported, double *PixelClockBackEnd) in PixelClockAdjustmentForProgressiveToInterlaceUnit() argument
435 …PixelClockBackEnd[k] = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].… in PixelClockAdjustmentForProgressiveToInterlaceUnit()
4220 double PixelClockBackEnd, in CalculateOutputLink() argument
4252 DML_LOG_VERBOSE("DML::%s: PixelClockBackEnd = %f\n", __func__, PixelClockBackEnd); in CalculateOutputLink()
4266 …ToValidBPP_locals, math_min2(600, PHYCLK) * 10, 3, HTotal, HActive, PixelClockBackEnd, ForcedOutpu… in CalculateOutputLink()
4291 …- Downspreading / 100) * 10000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutpu… in CalculateOutputLink()
4296 …- Downspreading / 100) * 10000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutpu… in CalculateOutputLink()
4304 …- Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutpu… in CalculateOutputLink()
4310 …- Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutpu… in CalculateOutputLink()
4318 …- Downspreading / 100) * 20000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutpu… in CalculateOutputLink()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.c706 mode_lib->vba.PixelClockBackEnd[mode_lib->vba.NumberOfActivePlanes] = dst->pixel_rate_mhz; in fetch_pipe_params()
1054 mode_lib->vba.PixelClockBackEnd[k] = mode_lib->vba.PixelClock[k]; in PixelClockAdjustmentForProgressiveToInterlaceUnit()
H A Ddisplay_mode_vba.h477 double PixelClockBackEnd[DC__NUM_DPP__MAX]; member