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Searched refs:PFIT_CONTROL (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/gma500/
H A Doaktrail_lvds.c133 REG_WRITE(PFIT_CONTROL, 0); in oaktrail_lvds_mode_set()
139 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); in oaktrail_lvds_mode_set()
143 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE | in oaktrail_lvds_mode_set()
146 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE | in oaktrail_lvds_mode_set()
149 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); in oaktrail_lvds_mode_set()
151 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); in oaktrail_lvds_mode_set()
H A Dpsb_intel_lvds.c269 lvds_priv->savePFIT_CONTROL = REG_READ(PFIT_CONTROL); in psb_intel_lvds_save()
310 REG_WRITE(PFIT_CONTROL, lvds_priv->savePFIT_CONTROL); in psb_intel_lvds_restore()
486 REG_WRITE(PFIT_CONTROL, pfit_control); in psb_intel_lvds_mode_set()
H A Doaktrail_device.c181 regs->psb.savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL); in oaktrail_save_display_registers()
305 PSB_WVDC32(regs->psb.savePFIT_CONTROL, PFIT_CONTROL); in oaktrail_restore_display_registers()
H A Dpsb_intel_display.c85 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
215 REG_WRITE(PFIT_CONTROL, 0); in psb_intel_crtc_mode_set()
H A Dcdv_device.c260 regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL); in cdv_save_display_registers()
331 REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL); in cdv_restore_display_registers()
H A Doaktrail_crtc.c352 pfit_control = REG_READ(PFIT_CONTROL); in oaktrail_panel_fitter_pipe()
428 REG_WRITE(PFIT_CONTROL, 0); in oaktrail_crtc_mode_set()
H A Dcdv_intel_display.c564 pfit_control = REG_READ(PFIT_CONTROL); in cdv_intel_panel_fitter_pipe()
763 REG_WRITE(PFIT_CONTROL, 0); in cdv_intel_crtc_mode_set()
H A Dcdv_intel_lvds.c294 REG_WRITE(PFIT_CONTROL, pfit_control); in cdv_intel_lvds_mode_set()
H A Dpsb_intel_reg.h205 #define PFIT_CONTROL 0x61230 macro
H A Dcdv_intel_dp.c1099 REG_WRITE(PFIT_CONTROL, pfit_control); in cdv_intel_dp_mode_set()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_pfit.c667 intel_de_read(display, PFIT_CONTROL(display)) & PFIT_ENABLE); in i9xx_pfit_enable()
672 intel_de_write(display, PFIT_CONTROL(display), in i9xx_pfit_enable()
692 intel_de_read(display, PFIT_CONTROL(display))); in i9xx_pfit_disable()
693 intel_de_write(display, PFIT_CONTROL(display), 0); in i9xx_pfit_disable()
715 tmp = intel_de_read(display, PFIT_CONTROL(display)); in i9xx_pfit_get_config()
H A Dintel_pfit_regs.h10 #define PFIT_CONTROL(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) macro
H A Dintel_lvds.c149 tmp = intel_de_read(display, PFIT_CONTROL(display)); in intel_lvds_get_config()
H A Dintel_overlay.c959 if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE) in update_pfit_vscale_ratio()