Searched refs:MT_WFDMA0 (Results 1 – 11 of 11) sorted by relevance
261 #define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs)) macro263 #define MT_WFDMA0_RST MT_WFDMA0(0x100)267 #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c)272 #define MT_MCU_CMD MT_WFDMA0(0x1f0)281 #define MT_MCU2HOST_SW_INT_ENA MT_WFDMA0(0x1f4)283 #define MT_WFDMA0_HOST_INT_STA MT_WFDMA0(0x200)290 #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)326 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)327 #define MT_WFDMA0_RST_DRX_PTR MT_WFDMA0(0x280)328 #define MT_WFDMA0_INT_RX_PRI MT_WFDMA0(0x298)[all …]
417 #define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs)) macro419 #define MT_WFDMA0_RST MT_WFDMA0(0x100)423 #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c)428 #define MT_WFDMA0_RX_INT_PCIE_SEL MT_WFDMA0(0x154)434 #define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4)436 #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)444 #define MT_WFDMA0_PAUSE_RX_Q_45_TH MT_WFDMA0(0x268)445 #define MT_WFDMA0_PAUSE_RX_Q_67_TH MT_WFDMA0(0x26c)446 #define MT_WFDMA0_PAUSE_RX_Q_89_TH MT_WFDMA0(0x270)447 #define MT_WFDMA0_PAUSE_RX_Q_RRO_TH MT_WFDMA0(0x27c)[all …]
246 __mt7996_dma_prefetch(dev, MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0)); in mt7996_dma_prefetch()254 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); in mt7996_dma_disable()301 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); in mt7996_dma_start()364 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); in mt7996_dma_enable()640 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); in mt7996_dma_init()912 u32 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); in mt7996_dma_reset()
37 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); in mt7996_npu_offload_init()
470 hif1_ofs = dev->hif2 ? MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0) : 0; in mt7996_mmio_wed_init()
673 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); in mt7996_register_phy()
31 #define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x204)32 #define MT_WFDMA0_HOST_INT_DIS MT_WFDMA0(0x22c)65 #define MT_RX_DATA_RING_BASE MT_WFDMA0(0x500)
31 #define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x204)61 #define MT_RX_DATA_RING_BASE MT_WFDMA0(0x520)
211 MT_RX_BUF_SIZE, MT_WFDMA0(0x540)); in mt7921_dma_init()
582 #define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs)) macro584 #define MT_WFDMA0_RST MT_WFDMA0(0x100)588 #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c)593 #define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4)595 #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)602 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)604 #define MT_WFDMA0_EXT0_CFG MT_WFDMA0(0x2b0)607 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)608 #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4)609 #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8)[all …]
169 __mt7915_dma_prefetch(dev, MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0)); in mt7915_dma_prefetch()178 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); in mt7915_dma_disable()262 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); in mt7915_dma_start()340 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); in mt7915_dma_enable()420 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); in mt7915_dma_init()