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Searched refs:MCR_REG (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_regs.h368 #define XEHP_PAT_INDEX(index) MCR_REG(_PAT_INDEX(index))
371 #define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900)
374 #define XEHP_FLAT_CCS_BASE_ADDR MCR_REG(0x4910)
417 #define GEN8_WM_CHICKEN2 MCR_REG(0x5584)
423 #define XEHP_CULLBIT1 MCR_REG(0x6100)
425 #define CHICKEN_RASTER_2 MCR_REG(0x6208)
428 #define VFLSKPD MCR_REG(0x62a8)
434 #define XEHP_FF_MODE2 MCR_REG(0x6604)
440 #define XEHPG_INSTDONE_GEOM_SVG MCR_REG(0x666c)
473 #define XEHP_CULLBIT2 MCR_REG(0x7030)
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/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_ads.c421 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL0)), false); in guc_mmio_regset_init()
422 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL1)), false); in guc_mmio_regset_init()
423 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL2)), false); in guc_mmio_regset_init()
424 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL3)), false); in guc_mmio_regset_init()
425 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL4)), false); in guc_mmio_regset_init()
426 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL5)), false); in guc_mmio_regset_init()
427 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL6)), false); in guc_mmio_regset_init()
/linux/drivers/gpu/drm/i915/
H A Di915_reg_defs.h197 #define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) }) macro