Searched refs:KVM_REG_RISCV_CSR (Results 1 – 4 of 4) sorted by relevance
144 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect): in filter_reg()145 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1): in filter_reg()146 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2): in filter_reg()147 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(sieh): in filter_reg()148 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siph): in filter_reg()149 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1h): in filter_reg()150 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2h): in filter_reg()397 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR); in csr_id_to_str()400 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR); in csr_id_to_str()773 case KVM_REG_RISCV_CSR: in print_reg()[all …]
606 KVM_REG_RISCV_CSR); in kvm_riscv_vcpu_get_reg_csr()645 KVM_REG_RISCV_CSR); in kvm_riscv_vcpu_set_reg_csr()935 u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_CSR | in copy_csr_reg_indices()952 u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_CSR | in copy_csr_reg_indices()970 u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_CSR | in copy_csr_reg_indices()1258 case KVM_REG_RISCV_CSR: in kvm_riscv_vcpu_set_reg()1291 case KVM_REG_RISCV_CSR: in kvm_riscv_vcpu_get_reg()
48 #define RISCV_GENERAL_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, \
262 #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT) macro