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Searched refs:FIELD_PREP (Results 1 – 25 of 1254) sorted by relevance

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/linux/drivers/accel/habanalabs/include/gaudi/
H A Dgaudi_masks.h15 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
16 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \
17 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF)))
20 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
21 (FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \
22 (FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \
23 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
26 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
27 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
30 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
[all …]
/linux/drivers/phy/microchip/
H A Dsparx5_serdes_regs.h51 FIELD_PREP(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
57 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
63 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)
74 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_ADV, x)
80 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)
86 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY, x)
92 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)
98 FIELD_PREP(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)
109 FIELD_PREP(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)
120 FIELD_PREP(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)
[all …]
H A Dlan966x_serdes_regs.h22 FIELD_PREP(HSIO_SD_CFG_PHY_RESET, x)
28 FIELD_PREP(HSIO_SD_CFG_TX_RESET, x)
34 FIELD_PREP(HSIO_SD_CFG_TX_RATE, x)
40 FIELD_PREP(HSIO_SD_CFG_TX_INVERT, x)
46 FIELD_PREP(HSIO_SD_CFG_TX_EN, x)
52 FIELD_PREP(HSIO_SD_CFG_TX_DATA_EN, x)
58 FIELD_PREP(HSIO_SD_CFG_TX_CM_EN, x)
64 FIELD_PREP(HSIO_SD_CFG_LANE_10BIT_SEL, x)
70 FIELD_PREP(HSIO_SD_CFG_RX_TERM_EN, x)
76 FIELD_PREP(HSIO_SD_CFG_RX_RESET, x)
[all …]
/linux/drivers/iio/adc/
H A Dstm32-dfsdm.h52 #define DFSDM_CHCFGR1_SITP(v) FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v)
54 #define DFSDM_CHCFGR1_SPICKSEL(v) FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v)
56 #define DFSDM_CHCFGR1_SCDEN(v) FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v)
58 #define DFSDM_CHCFGR1_CKABEN(v) FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v)
60 #define DFSDM_CHCFGR1_CHEN(v) FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v)
62 #define DFSDM_CHCFGR1_CHINSEL(v) FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v)
64 #define DFSDM_CHCFGR1_DATMPX(v) FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v)
66 #define DFSDM_CHCFGR1_DATPACK(v) FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v)
68 #define DFSDM_CHCFGR1_CKOUTDIV(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v)
70 #define DFSDM_CHCFGR1_CKOUTSRC(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTSRC_MASK, v)
[all …]
/linux/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_regs.h39 FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)
48 FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)
54 FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x)
63 FIELD_PREP(ANA_ADVLEARN_VLAN_CHK, x)
75 FIELD_PREP(ANA_ANAINTR_INTR, x)
81 FIELD_PREP(ANA_ANAINTR_INTR_ENA, x)
90 FIELD_PREP(ANA_AUTOAGE_AGE_PERIOD, x)
99 FIELD_PREP(ANA_MIRRORPORTS_MIRRORPORTS, x)
108 FIELD_PREP(ANA_EMIRRORPORTS_EMIRRORPORTS, x)
117 FIELD_PREP(ANA_FLOODING_FLD_UNICAST, x)
[all …]
/linux/drivers/crypto/inside-secure/eip93/
H A Deip93-regs.h102 #define EIP93_PE_TARGET_AUTO_RING_MODE FIELD_PREP(EIP93_PE_CONFIG_PE_MODE, 0x3)
103 #define EIP93_PE_TARGET_COMMAND_NO_RDR_MODE FIELD_PREP(EIP93_PE_CONFIG_PE_MODE, 0x2)
104 #define EIP93_PE_TARGET_COMMAND_WITH_RDR_MODE FIELD_PREP(EIP93_PE_CONFIG_PE_MODE, 0x1)
105 #define EIP93_PE_DIRECT_HOST_MODE FIELD_PREP(EIP93_PE_CONFIG_PE_MODE, 0x0)
202 #define EIP93_SA_CMD_HASH_NO_LOAD FIELD_PREP(EIP93_SA_CMD_HASH_SOURCE, 0x3)
203 #define EIP93_SA_CMD_HASH_FROM_STATE FIELD_PREP(EIP93_SA_CMD_HASH_SOURCE, 0x2)
204 #define EIP93_SA_CMD_HASH_FROM_SA FIELD_PREP(EIP93_SA_CMD_HASH_SOURCE, 0x0)
206 #define EIP93_SA_CMD_IV_FROM_PRNG FIELD_PREP(EIP93_SA_CMD_IV_SOURCE, 0x3)
207 #define EIP93_SA_CMD_IV_FROM_STATE FIELD_PREP(EIP93_SA_CMD_IV_SOURCE, 0x2)
208 #define EIP93_SA_CMD_IV_FROM_INPUT FIELD_PREP(EIP93_SA_CMD_IV_SOURCE, 0x1)
[all …]
/linux/drivers/tty/serial/
H A Datmel_serial.h44 #define ATMEL_US_USMODE_NORMAL FIELD_PREP(ATMEL_US_USMODE, 0)
45 #define ATMEL_US_USMODE_RS485 FIELD_PREP(ATMEL_US_USMODE, 1)
46 #define ATMEL_US_USMODE_HWHS FIELD_PREP(ATMEL_US_USMODE, 2)
47 #define ATMEL_US_USMODE_MODEM FIELD_PREP(ATMEL_US_USMODE, 3)
48 #define ATMEL_US_USMODE_ISO7816_T0 FIELD_PREP(ATMEL_US_USMODE, 4)
49 #define ATMEL_US_USMODE_ISO7816_T1 FIELD_PREP(ATMEL_US_USMODE, 6)
50 #define ATMEL_US_USMODE_IRDA FIELD_PREP(ATMEL_US_USMODE, 8)
52 #define ATMEL_US_USCLKS_MCK FIELD_PREP(ATMEL_US_USCLKS, 0)
53 #define ATMEL_US_USCLKS_MCK_DIV8 FIELD_PREP(ATMEL_US_USCLKS, 1)
54 #define ATMEL_US_USCLKS_GCLK FIELD_PREP(ATMEL_US_USCLKS, 2)
[all …]
/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main_regs.h83 FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x)
89 FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
100 FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x)
111 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x)
117 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x)
123 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VID, x)
129 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x)
135 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x)
141 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x)
164 FIELD_PREP(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x)
[all …]
/linux/drivers/infiniband/hw/irdma/
H A Duda.c31 qw1 = FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_PDINDEXLO, info->pd_idx) | in irdma_sc_access_ah()
32 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_TC, info->tc_tos) | in irdma_sc_access_ah()
33 FIELD_PREP(IRDMA_UDAQPC_VLANTAG, info->vlan_tag); in irdma_sc_access_ah()
35 qw2 = FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ARPINDEX, info->dst_arpindex) | in irdma_sc_access_ah()
36 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_FLOWLABEL, info->flow_label) | in irdma_sc_access_ah()
37 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_HOPLIMIT, info->hop_ttl) | in irdma_sc_access_ah()
38 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_PDINDEXHI, info->pd_idx >> 16); in irdma_sc_access_ah()
42 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR0, info->dest_ip_addr[0]) | in irdma_sc_access_ah()
43 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR1, info->dest_ip_addr[1])); in irdma_sc_access_ah()
45 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR2, info->dest_ip_addr[2]) | in irdma_sc_access_ah()
[all …]
H A Dctrl.c204 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) | in irdma_sc_add_arp_cache_entry()
205 FIELD_PREP(IRDMA_CQPSQ_MAT_PERMANENT, (info->permanent ? 1 : 0)) | in irdma_sc_add_arp_cache_entry()
206 FIELD_PREP(IRDMA_CQPSQ_MAT_ENTRYVALID, 1) | in irdma_sc_add_arp_cache_entry()
207 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); in irdma_sc_add_arp_cache_entry()
238 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) | in irdma_sc_del_arp_cache_entry()
239 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); in irdma_sc_del_arp_cache_entry()
273 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_APBVT) | in irdma_sc_manage_apbvt_entry()
274 FIELD_PREP(IRDMA_CQPSQ_MAPT_ADDPORT, info->add) | in irdma_sc_manage_apbvt_entry()
275 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); in irdma_sc_manage_apbvt_entry()
324 qw1 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QPN, info->qp_num) | in irdma_sc_manage_qhash_table_entry()
[all …]
H A Duk.c20 FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->addr)); in irdma_set_fragment()
22 FIELD_PREP(IRDMAQPSQ_VALID, valid) | in irdma_set_fragment()
23 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, sge->length) | in irdma_set_fragment()
24 FIELD_PREP(IRDMAQPSQ_FRAG_STAG, sge->lkey)); in irdma_set_fragment()
28 FIELD_PREP(IRDMAQPSQ_VALID, valid)); in irdma_set_fragment()
44 FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->addr)); in irdma_set_fragment_gen_1()
46 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, sge->length) | in irdma_set_fragment_gen_1()
47 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, sge->lkey)); in irdma_set_fragment_gen_1()
77 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) | in irdma_nop_1()
78 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, signaled) | in irdma_nop_1()
[all …]
/linux/drivers/net/wireless/ath/ath11k/
H A Dhal_tx.c43 FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, ti->paddr); in ath11k_hal_tx_cmd_desc_setup()
45 FIELD_PREP(BUFFER_ADDR_INFO1_ADDR, in ath11k_hal_tx_cmd_desc_setup()
48 FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR, ti->rbm_id) | in ath11k_hal_tx_cmd_desc_setup()
49 FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, ti->desc_id); in ath11k_hal_tx_cmd_desc_setup()
52 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_DESC_TYPE, ti->type) | in ath11k_hal_tx_cmd_desc_setup()
53 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE, ti->encap_type) | in ath11k_hal_tx_cmd_desc_setup()
54 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE, in ath11k_hal_tx_cmd_desc_setup()
56 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE, in ath11k_hal_tx_cmd_desc_setup()
58 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ADDR_EN, in ath11k_hal_tx_cmd_desc_setup()
60 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_CMD_NUM, in ath11k_hal_tx_cmd_desc_setup()
[all …]
H A Dhal_rx.c17 hdr->info0 = FIELD_PREP(HAL_DESC_HDR_INFO0_OWNER, owner) | in ath11k_hal_reo_set_desc_hdr()
18 FIELD_PREP(HAL_DESC_HDR_INFO0_BUF_TYPE, buffer_type); in ath11k_hal_reo_set_desc_hdr()
21 hdr->info0 |= FIELD_PREP(HAL_DESC_HDR_INFO0_DBG_RESERVED, magic); in ath11k_hal_reo_set_desc_hdr()
29 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_GET_QUEUE_STATS) | in ath11k_hal_reo_cmd_queue_stats()
30 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); in ath11k_hal_reo_cmd_queue_stats()
40 desc->info0 = FIELD_PREP(HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI, in ath11k_hal_reo_cmd_queue_stats()
61 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_FLUSH_CACHE) | in ath11k_hal_reo_cmd_flush_cache()
62 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); in ath11k_hal_reo_cmd_flush_cache()
72 desc->info0 = FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI, in ath11k_hal_reo_cmd_flush_cache()
81 FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX, in ath11k_hal_reo_cmd_flush_cache()
[all …]
/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_mipi_dsi_regs.h44 #define TXCMPHDR_VC(n) FIELD_PREP(TXCMPHDR_VC_MASK, (n))
46 #define TXCMPHDR_DT(n) FIELD_PREP(TXCMPHDR_DT_MASK, (n))
48 #define TXCMPHDR_DATA1(n) FIELD_PREP(TXCMPHDR_DATA1_MASK, (n))
50 #define TXCMPHDR_DATA0(n) FIELD_PREP(TXCMPHDR_DATA0_MASK, (n))
171 #define TXVMPSPHSETR_DT_RGB16 FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x0e)
172 #define TXVMPSPHSETR_DT_RGB18 FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x1e)
173 #define TXVMPSPHSETR_DT_RGB18_LS FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x2e)
174 #define TXVMPSPHSETR_DT_RGB24 FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x3e)
175 #define TXVMPSPHSETR_DT_YCBCR16 FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x2c)
182 #define TXVMVPRMSET0R_BPP_16 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 0)
[all …]
/linux/drivers/phy/amlogic/
H A Dphy-meson-g12a-usb2.c193 FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) | in phy_meson_g12a_usb2_init()
194 FIELD_PREP(PHY_CTRL_R16_MPLL_N, 1) | in phy_meson_g12a_usb2_init()
196 FIELD_PREP(PHY_CTRL_R16_MPLL_LOCK_LONG, 1) | in phy_meson_g12a_usb2_init()
202 FIELD_PREP(PHY_CTRL_R17_MPLL_FRAC_IN, 0) | in phy_meson_g12a_usb2_init()
203 FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA1, 7) | in phy_meson_g12a_usb2_init()
204 FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA0, 7) | in phy_meson_g12a_usb2_init()
205 FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) | in phy_meson_g12a_usb2_init()
206 FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9)); in phy_meson_g12a_usb2_init()
208 value = FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) | in phy_meson_g12a_usb2_init()
209 FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) | in phy_meson_g12a_usb2_init()
[all …]
/linux/drivers/crypto/ccree/
H A Dcc_hw_queue_defs.h224 pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1); in set_queue_last_ind_bit()
242 pdesc->word[5] |= FIELD_PREP(WORD5_DIN_ADDR_HIGH, upper_32_bits(addr)); in set_din_type()
244 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_DMA_MODE, dma_mode) | in set_din_type()
245 FIELD_PREP(WORD1_DIN_SIZE, size) | in set_din_type()
246 FIELD_PREP(WORD1_NS_BIT, axi_sec); in set_din_type()
260 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size); in set_din_no_dma()
273 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, CC_CPP_DIN_SIZE); in set_cpp_crypto_key()
274 pdesc->word[1] |= FIELD_PREP(WORD1_LOCK_QUEUE, 1); in set_cpp_crypto_key()
276 pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, slot); in set_cpp_crypto_key()
291 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size) | in set_din_sram()
[all …]
/linux/drivers/phy/starfive/
H A Dphy-jh7110-dphy-tx.c78 #define STF_DPHY_LSHIFT_16(x) (FIELD_PREP(GENMASK(23, 16), (x)))
79 #define STF_DPHY_LSHIFT_8(x) (FIELD_PREP(GENMASK(15, 8), (x)))
217 writel(FIELD_PREP(STF_DPHY_RESETB, assert), in stf_dphy_hw_reset()
248 tmp |= FIELD_PREP(STF_DPHY_REFCLK_IN_SEL, STF_DPHY_REFCLK_12M); in stf_dphy_configure()
251 writel(FIELD_PREP(STF_DPHY_RG_CDTX_L0N_HSTX_RES, 0x10) | in stf_dphy_configure()
252 FIELD_PREP(STF_DPHY_RG_CDTX_L0P_HSTX_RES, 0x10), in stf_dphy_configure()
255 writel(FIELD_PREP(STF_DPHY_RG_CDTX_L0N_HSTX_RES, 0x10) | in stf_dphy_configure()
256 FIELD_PREP(STF_DPHY_RG_CDTX_L2N_HSTX_RES, 0x10) | in stf_dphy_configure()
257 FIELD_PREP(STF_DPHY_RG_CDTX_L3N_HSTX_RES, 0x10) | in stf_dphy_configure()
258 FIELD_PREP(STF_DPHY_RG_CDTX_L1P_HSTX_RES, 0x10) | in stf_dphy_configure()
[all …]
/linux/drivers/net/ethernet/meta/fbnic/
H A Dfbnic_mac.c21 val |= FIELD_PREP(FBNIC_QM_TNI_TDF_CTL_MRRS, readrq) | in fbnic_init_readrq()
22 FIELD_PREP(FBNIC_QM_TNI_TDF_CTL_CLS, cls); in fbnic_init_readrq()
35 val |= FIELD_PREP(FBNIC_QM_TNI_TCM_CTL_MPS, mps) | in fbnic_init_mps()
36 FIELD_PREP(FBNIC_QM_TNI_TCM_CTL_CLS, cls); in fbnic_init_mps()
73 FIELD_PREP(FBNIC_QM_TNI_TDE_CTL_MRRS_1K, override_1k ? 1 : 0) | in fbnic_mac_init_axi()
74 FIELD_PREP(FBNIC_QM_TNI_TDE_CTL_MAX_OB, 704) | in fbnic_mac_init_axi()
75 FIELD_PREP(FBNIC_QM_TNI_TDE_CTL_MAX_OT, 128) | in fbnic_mac_init_axi()
76 FIELD_PREP(FBNIC_QM_TNI_TDE_CTL_MRRS, readrq) | in fbnic_mac_init_axi()
77 FIELD_PREP(FBNIC_QM_TNI_TDE_CTL_CLS, cls)); in fbnic_mac_init_axi()
86 u64 default_meta = FIELD_PREP(FBNIC_TWD_L2_HLEN_MASK, ETH_HLEN) | in fbnic_mac_init_qm()
[all …]
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-samsung-hdptx.c1145 FIELD_PREP(LCPLL_EN_MASK, 1) | in rk_hdptx_frl_lcpll_cmn_config()
1146 FIELD_PREP(LCPLL_LCVCO_MODE_EN_MASK, cfg->lcvco_mode_en)); in rk_hdptx_frl_lcpll_cmn_config()
1150 FIELD_PREP(LCPLL_PI_EN_MASK, cfg->pi_en) | in rk_hdptx_frl_lcpll_cmn_config()
1151 FIELD_PREP(LCPLL_100M_CLK_EN_MASK, cfg->clk_en_100m)); in rk_hdptx_frl_lcpll_cmn_config()
1164 FIELD_PREP(LCPLL_SDC_N_MASK, cfg->sdc_n)); in rk_hdptx_frl_lcpll_cmn_config()
1167 FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv)); in rk_hdptx_frl_lcpll_cmn_config()
1169 FIELD_PREP(PLL_PCG_CLK_SEL_MASK, (hdptx->hdmi_cfg.bpc - 8) >> 1)); in rk_hdptx_frl_lcpll_cmn_config()
1233 FIELD_PREP(ROPLL_SDM_EN_MASK, cfg->sdm_en)); in rk_hdptx_tmds_ropll_cmn_config()
1238 FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, cfg->sdm_num_sign)); in rk_hdptx_tmds_ropll_cmn_config()
1244 FIELD_PREP(ROPLL_SDC_N_RBR_MASK, cfg->sdc_n)); in rk_hdptx_tmds_ropll_cmn_config()
[all …]
/linux/drivers/net/dsa/
H A Dyt921x.h12 #define YT921X_SMI_SWITCHID(x) FIELD_PREP(YT921X_SMI_SWITCHID_M, (x))
33 #define YT921X_EXT_CPU_PORT_PORT(x) FIELD_PREP(YT921X_EXT_CPU_PORT_PORT_M, (x))
47 #define YT9215_IO_LEVEL_NORMAL(x) FIELD_PREP(YT9215_IO_LEVEL_NORMAL_M, (x))
51 #define YT9215_IO_LEVEL_RGMII1(x) FIELD_PREP(YT9215_IO_LEVEL_RGMII1_M, (x))
56 #define YT9215_IO_LEVEL_RGMII0(x) FIELD_PREP(YT9215_IO_LEVEL_RGMII0_M, (x))
61 #define YT9218_IO_LEVEL_RGMII1(x) FIELD_PREP(YT9218_IO_LEVEL_RGMII1_M, (x))
66 #define YT9218_IO_LEVEL_RGMII0(x) FIELD_PREP(YT9218_IO_LEVEL_RGMII0_M, (x))
71 #define YT9218_IO_LEVEL_NORMAL(x) FIELD_PREP(YT9218_IO_LEVEL_NORMAL_M, (x))
78 #define YT921X_SERDES_MODE(x) FIELD_PREP(YT921X_SERDES_MODE_M, (x))
89 #define YT921X_SERDES_SPEED(x) FIELD_PREP(YT921X_SERDES_SPEED_M, (x))
[all …]
/linux/drivers/i3c/master/mipi-i3c-hci/
H A Dcmd_v1.c22 #define CMD_0_ATTR_A FIELD_PREP(CMD_0_ATTR, 0x2)
26 #define CMD_A0_DEV_COUNT(v) FIELD_PREP(W0_MASK(29, 26), v)
27 #define CMD_A0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v)
28 #define CMD_A0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v)
29 #define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
35 #define CMD_0_ATTR_I FIELD_PREP(CMD_0_ATTR, 0x1)
37 #define CMD_I1_DATA_BYTE_4(v) FIELD_PREP(W1_MASK(63, 56), v)
38 #define CMD_I1_DATA_BYTE_3(v) FIELD_PREP(W1_MASK(55, 48), v)
39 #define CMD_I1_DATA_BYTE_2(v) FIELD_PREP(W1_MASK(47, 40), v)
40 #define CMD_I1_DATA_BYTE_1(v) FIELD_PREP(W1_MASK(39, 32), v)
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-mediatek.c186 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->tx_delay); in mt2712_set_delay()
187 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->tx_delay); in mt2712_set_delay()
188 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->tx_inv); in mt2712_set_delay()
190 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); in mt2712_set_delay()
191 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); in mt2712_set_delay()
192 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
201 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay); in mt2712_set_delay()
202 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay); in mt2712_set_delay()
203 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
205 delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay); in mt2712_set_delay()
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_overlay.c29 #define VD_HOLD_LINES(lines) FIELD_PREP(GENMASK(24, 19), lines)
31 #define VD_BYTES_PER_PIXEL(val) FIELD_PREP(GENMASK(15, 14), val)
38 #define CANVAS_ADDR2(addr) FIELD_PREP(GENMASK(23, 16), addr)
39 #define CANVAS_ADDR1(addr) FIELD_PREP(GENMASK(15, 8), addr)
40 #define CANVAS_ADDR0(addr) FIELD_PREP(GENMASK(7, 0), addr)
43 #define VD_X_START(value) FIELD_PREP(GENMASK(14, 0), value)
44 #define VD_X_END(value) FIELD_PREP(GENMASK(30, 16), value)
47 #define VD_Y_START(value) FIELD_PREP(GENMASK(12, 0), value)
48 #define VD_Y_END(value) FIELD_PREP(GENMASK(28, 16), value)
51 #define VD_COLOR_MAP(value) FIELD_PREP(GENMASK(1, 0), value)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dinit.c28 [1] = FIELD_PREP(MT_TXD3_REM_TX_COUNT, 0xf), in mt7603_set_tmac_template()
61 FIELD_PREP(MT_PSE_FRP_P0, 7) | in mt7603_dma_sched_init()
62 FIELD_PREP(MT_PSE_FRP_P1, 6) | in mt7603_dma_sched_init()
63 FIELD_PREP(MT_PSE_FRP_P2_RQ2, 4)); in mt7603_dma_sched_init()
123 (FIELD_PREP(MT_WF_RMAC_RMCR_SMPS_MODE, 3) | in mt7603_phy_init()
124 FIELD_PREP(MT_WF_RMAC_RMCR_RX_STREAMS, rx_chains))); in mt7603_phy_init()
153 FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) | in mt7603_mac_init()
154 FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) | in mt7603_mac_init()
155 FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) | in mt7603_mac_init()
156 FIELD_PREP(MT_AGG_LIMIT_AC(3), 24)); in mt7603_mac_init()
[all …]
/linux/drivers/firmware/samsung/
H A Dexynos-acpm-pmic.c73 cmd[0] = FIELD_PREP(ACPM_PMIC_TYPE, type) | in acpm_pmic_init_read_cmd()
74 FIELD_PREP(ACPM_PMIC_REG, reg) | in acpm_pmic_init_read_cmd()
75 FIELD_PREP(ACPM_PMIC_CHANNEL, chan); in acpm_pmic_init_read_cmd()
76 cmd[1] = FIELD_PREP(ACPM_PMIC_FUNC, ACPM_PMIC_READ); in acpm_pmic_init_read_cmd()
103 cmd[0] = FIELD_PREP(ACPM_PMIC_TYPE, type) | in acpm_pmic_init_bulk_read_cmd()
104 FIELD_PREP(ACPM_PMIC_REG, reg) | in acpm_pmic_init_bulk_read_cmd()
105 FIELD_PREP(ACPM_PMIC_CHANNEL, chan); in acpm_pmic_init_bulk_read_cmd()
106 cmd[1] = FIELD_PREP(ACPM_PMIC_FUNC, ACPM_PMIC_BULK_READ) | in acpm_pmic_init_bulk_read_cmd()
107 FIELD_PREP(ACPM_PMIC_VALUE, count); in acpm_pmic_init_bulk_read_cmd()
145 cmd[0] = FIELD_PREP(ACPM_PMIC_TYPE, type) | in acpm_pmic_init_write_cmd()
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