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Searched refs:DP_DSC_RECEIVER_CAP_SIZE (Results 1 – 4 of 4) sorted by relevance

/linux/include/drm/display/
H A Ddrm_dp_helper.h208 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
210 u32 drm_dp_dsc_sink_slice_count_mask(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
212 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
214 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
215 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
217 int drm_dp_dsc_sink_max_slice_throughput(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
224 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in drm_dp_sink_supports_dsc() argument
231 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in drm_edp_dsc_sink_output_bpp() argument
239 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in drm_dp_dsc_sink_max_slice_width() argument
254 drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format) in drm_dp_dsc_sink_supports_format() argument
H A Ddrm_dp.h1692 #define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */ macro
/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_types.h557 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
H A Dintel_dp.c1872 static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in intel_dp_sink_dsc_version_minor() argument
4297 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in intel_dp_read_dsc_dpcd() argument
4300 DP_DSC_RECEIVER_CAP_SIZE) < 0) { in intel_dp_read_dsc_dpcd()
4308 DP_DSC_RECEIVER_CAP_SIZE, in intel_dp_read_dsc_dpcd()