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Searched refs:DPIO_CH1 (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/i915/display/ !
H A Dintel_display_power_well.c1380 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | in assert_chv_phy_status()
1381 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | in assert_chv_phy_status()
1382 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); in assert_chv_phy_status()
1396 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) in assert_chv_phy_status()
1397 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); in assert_chv_phy_status()
1402 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) in assert_chv_phy_status()
1411 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && in assert_chv_phy_status()
1413 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); in assert_chv_phy_status()
1423 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) in assert_chv_phy_status()
1424 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); in assert_chv_phy_status()
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H A Dintel_dpio_phy.c177 [DPIO_CH1] = { .port = PORT_C },
264 port == phy_info->channel[DPIO_CH1].port) { in bxt_port_to_phy_channel()
266 *ch = DPIO_CH1; in bxt_port_to_phy_channel()
669 return DPIO_CH1; in vlv_dig_port_to_channel()
711 return DPIO_CH1; in vlv_pipe_to_channel()
886 !chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, true); in chv_phy_pre_pll_enable()
901 if (ch == DPIO_CH1) in chv_phy_pre_pll_enable()
909 if (ch == DPIO_CH1) in chv_phy_pre_pll_enable()
1032 chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, false); in chv_phy_release_cl2_override()
H A Dintel_dpio_phy.h20 DPIO_CH1, enumerator
/linux/drivers/gpu/drm/i915/gvt/ !
H A Dhandlers.c576 ch = DPIO_CH1; in bxt_vgpu_get_dp_bitrate()
2802 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, in init_bxt_mmio_info()
2804 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT, in init_bxt_mmio_info()