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/linux/Documentation/devicetree/bindings/mips/brcm/
H A Dsoc.txt45 independently (control registers, DDR PHYs, etc.). One might consider
58 the entire memory controller (including all sub nodes: DDR PHY,
86 == DDR PHY control
88 Control registers for this memory controller's DDR PHY.
95 - reg : the DDR PHY register range and length
104 == DDR memory controller sequencer
106 Control registers for this memory controller's DDR memory sequencer
115 - reg : the DDR sequencer register range and length
136 - reg : the DDR Arbiter register range and length
/linux/Documentation/admin-guide/perf/
H A Dmeson-ddr-pmu.rst4 Amlogic SoC DDR Bandwidth Performance Monitoring Unit (PMU)
10 to show if the performance bottleneck is on DDR bandwidth.
24 Below are DDR access request event filter keywords:
55 + Show the total DDR bandwidth per seconds:
62 + Show individual DDR bandwidth from CPU and GPU respectively, as well as
H A Dalibaba_pmu.rst9 DDR Sub-System Driveway (DRW) PMU Driver
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
43 The DDR Controller (DDRCTL) and DDR PHY combine to create a complete solution
44 for connecting an SoC application bus to DDR memory devices. The DDRCTL
49 the DDR PHY Interface (DFI) to the PHY module, which launches and captures data
H A Dmrvl-odyssey-ddr-pmu.rst2 Marvell Odyssey DDR PMU Performance Monitoring Unit (PMU UNCORE)
8 at the interface between the DDR controller and the PHY, interface between
9 the DDR Controller and the CHI interconnect, or within the DDR Controller.
H A Dimx-ddr.rst2 Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
21 in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
69 counting the number of bytes (as opposed to the number of bursts) from DDR
87 PMU in DDR subsystem, only one single port0 exists, so axi_port is reserved
99 monitor data channel from DDR transactions, since data channel is more
/linux/Documentation/ABI/testing/
H A Dsysfs-driver-bd9571mwv-regulator5 Description: Read/write the current state of DDR Backup Mode, which controls
6 if DDR power rails will be kept powered during system suspend.
10 A. With a momentary power switch (or pulse signal), DDR
26 DDR Backup Mode must be explicitly enabled by the user,
H A Dsysfs-platform-brcmstb-memc7 internal DDR controller clock cycles. Possible values range
15 DDR PHY frequency in Hz.
/linux/drivers/gpio/
H A Dgpio-mb86s7x.c30 #define DDR(x) (0x10 + x / 8 * 4) macro
81 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
83 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
106 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
108 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
/linux/Documentation/devicetree/bindings/arm/bcm/
H A Dbrcm,brcmstb.txt148 independently (control registers, DDR PHYs, etc.). One might consider
163 == DDR PHY control
165 Control registers for this memory controller's DDR PHY.
175 - reg : the DDR PHY register range
177 == DDR SHIMPHY
179 Control registers for this memory controller's DDR SHIMPHY.
183 - reg : the DDR SHIMPHY register range
185 == MEMC DDR control
/linux/Documentation/driver-api/thermal/
H A Dintel_dptf.rst228 DDR (Double Data Rate) and DLVR (Digital Linear Voltage Regulator)
249 DRAM devices of DDR IO interface and their power plane can generate EMI
251 mechanism by which DDR data rates can be changed if several conditions
252 are met: there is strong RFI interference because of DDR; CPU power
253 management has no other restriction in changing DDR data rates;
254 PC ODMs enable this feature (real time DDR RFI Mitigation referred to as
255 DDR-RFIM) for Wi-Fi from BIOS.
289 Request the restriction of specific DDR data rate and set this
297 Restricted DDR data rate for RFI protection: Lower Limit
300 Restricted DDR data rate for RFI protection: Upper Limit
[all …]
/linux/drivers/perf/amlogic/
H A DKconfig3 tristate "Amlogic DDR Bandwidth Performance Monitor"
6 Provides support for the DDR performance monitor
/linux/drivers/mtd/lpddr/
H A DKconfig10 flash chips. Synonymous with Mobile-DDR. It is a new standard for
11 DDR memories, intended for battery-operated systems.
/linux/arch/arm/mach-omap2/
H A Dsleep24xx.S55 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
75 movs r0, r0 @ see if DDR or SDR
/linux/Documentation/accel/qaic/
H A Daic100.rst17 Each SoC has an A53 management CPU. On card, there can be up to 32 GB of DDR.
26 An AIC100 card consists of an AIC100 SoC, on-card DDR, and a set of misc
60 * DDR
99 DDR section in Hardware Description
102 AIC100 has on-card DDR. In total, an AIC100 can have up to 32 GB of DDR.
103 This DDR is used to store workloads, data for the workloads, and is used by the
104 QSM for managing the device. NSPs are granted access to sections of the DDR by
105 the QSM. The host does not have direct access to the DDR, and must make
106 requests to the QSM to transfer data to the DDR.
120 device DDR
[all …]
/linux/drivers/perf/
H A DKconfig166 tristate "Freescale i.MX8 DDR perf monitor"
169 Provides support for the DDR performance monitor in i.MX8, which
174 tristate "Freescale i.MX9 DDR perf monitor"
177 Provides support for the DDR performance monitor in i.MX9, which
268 tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver"
271 Support for Driveway PMU events monitoring on Yitian 710 DDR
280 Enable perf support for Marvell DDR Performance monitoring
/linux/drivers/edac/
H A DKconfig311 tristate "Freescale Layerscape DDR"
466 bool "Marvell Armada XP DDR and L2 Cache ECC"
470 DDR RAM and L2 cache controllers.
473 tristate "Synopsys DDR Memory Controller"
476 Support for error detection and correction on the Synopsys DDR
538 tristate "Nuvoton NPCM DDR Memory Controller"
541 Support for error detection and correction on the Nuvoton NPCM DDR
549 tristate "Xilinx Versal DDR Memory Controller"
552 Support for error detection and correction on the Xilinx Versal DDR
577 tristate "AMD VersalNET DDR Controller"
[all …]
/linux/drivers/memory/
H A DKconfig11 for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features
17 config DDR config
20 Data from JEDEC specs for DDR SDRAM memories,
23 DDR SDRAM controllers.
52 STB SoCs. The firmware running on the DCPU inside the DDR PHY can
93 select DDR
/linux/Documentation/driver-api/memory-devices/
H A Dti-emif.rst38 DDR device details and other board dependent and SoC dependent
41 - DDR device details: 'struct ddr_device_info'
/linux/drivers/memory/tegra/
H A DKconfig19 select DDR
31 select DDR
/linux/Documentation/devicetree/bindings/mips/img/
H A Dxilfpga.txt20 - 128Mbyte DDR RAM at 0x0000_0000
74 DDR initialization is already handled by a HW IP block.
/linux/drivers/clk/sophgo/
H A DKconfig20 PLL, DDR PLL 0 and DDR PLL 1 respectively.
/linux/drivers/clk/baikal-t1/
H A DKconfig27 CPUs, DDR, etc.) or passed over the clock dividers to be only
50 can be directly asserted/de-asserted (PCIe and DDR sub-domains).
/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra30.c2200 …PINGROUP(vi_d1_pd5, DDR, SDMMC2, VI, RSVD4, 0x3128, N, …
2201 …PINGROUP(vi_vsync_pd6, DDR, RSVD2, VI, RSVD4, 0x315c, N, …
2202 …PINGROUP(vi_hsync_pd7, DDR, RSVD2, VI, RSVD4, 0x3160, N, …
2259 …PINGROUP(vi_d2_pl0, DDR, SDMMC2, VI, RSVD4, 0x312c, N, …
2260 …PINGROUP(vi_d3_pl1, DDR, SDMMC2, VI, RSVD4, 0x3130, N, …
2261 …PINGROUP(vi_d4_pl2, DDR, SDMMC2, VI, RSVD4, 0x3134, N, …
2262 …PINGROUP(vi_d5_pl3, DDR, SDMMC2, VI, RSVD4, 0x3138, N, …
2263 …PINGROUP(vi_d6_pl4, DDR, SDMMC2, VI, RSVD4, 0x313c, N, …
2264 …PINGROUP(vi_d7_pl5, DDR, SDMMC2, VI, RSVD4, 0x3140, N, …
2265 …PINGROUP(vi_d8_pl6, DDR, SDMMC2, VI, RSVD4, 0x3144, N, …
[all …]
/linux/drivers/accel/qaic/
H A Dqaic_ras.c49 DDR, enumerator
59 [DDR] = "DDR",
236 case DDR: in ras_msg_to_cpu()
383 case DDR: in decode_ras_msg()
/linux/arch/mips/include/asm/mach-loongson2ef/
H A Dloongson.h321 LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
323 LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)

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