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Searched refs:CP_ME_CNTL (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2703 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2706 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2712 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2715 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2826 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
2829 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
2835 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
2838 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
2986 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); in gfx_v11_0_config_gfx_rs64()
2987 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); in gfx_v11_0_config_gfx_rs64()
[all …]
H A Dgfx_v12_0.c2136 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); in gfx_v12_0_config_gfx_rs64()
2137 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); in gfx_v12_0_config_gfx_rs64()
2141 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); in gfx_v12_0_config_gfx_rs64()
2142 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); in gfx_v12_0_config_gfx_rs64()
2158 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); in gfx_v12_0_config_gfx_rs64()
2159 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); in gfx_v12_0_config_gfx_rs64()
2163 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); in gfx_v12_0_config_gfx_rs64()
2164 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); in gfx_v12_0_config_gfx_rs64()
2216 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v12_0_set_pfp_ucode_start_addr()
2219 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v12_0_set_pfp_ucode_start_addr()
[all …]
H A Dgfx_v10_0.c6078 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); in gfx_v10_0_cp_gfx_enable()
6079 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); in gfx_v10_0_cp_gfx_enable()
6080 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); in gfx_v10_0_cp_gfx_enable()
/linux/drivers/gpu/drm/radeon/
H A Dni.c1438 WREG32(CP_ME_CNTL, 0); in cayman_cp_enable()
1442 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); in cayman_cp_enable()
1820 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in cayman_gpu_soft_reset()
H A Drv770d.h335 #define CP_ME_CNTL 0x86D8 macro
H A Dnid.h318 #define CP_ME_CNTL 0x86D8 macro
H A Dsid.h1027 #define CP_ME_CNTL 0x86D8 macro
H A Dcikd.h1108 #define CP_ME_CNTL 0x86D8 macro
H A Dsi.c3443 WREG32(CP_ME_CNTL, 0); in si_cp_enable()
3447 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in si_cp_enable()
3860 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in si_gpu_soft_reset()
4029 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in si_gpu_pci_config_reset()
H A Drv770.c1084 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); in r700_cp_stop()
H A Devergreend.h461 #define CP_ME_CNTL 0x86D8 macro
H A Dcik.c3866 WREG32(CP_ME_CNTL, 0); in cik_cp_gfx_enable()
3870 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in cik_cp_gfx_enable()
4947 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_soft_reset()
5151 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_pci_config_reset()