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Searched refs:CP_ME1_PIPE0_INT_CNTL (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c6397 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
6399 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
6405 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
6407 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
6530 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_priv_reg_fault_state()
6576 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_bad_op_fault_state()
6717 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
6727 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
H A Dgfx_v12_0.c4763 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_compute_eop_interrupt_state()
4765 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_compute_eop_interrupt_state()
4771 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_compute_eop_interrupt_state()
4773 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_compute_eop_interrupt_state()
4896 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_priv_reg_fault_state()
4942 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_bad_op_fault_state()
H A Dgfx_v10_0.c9121 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
9127 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
9249 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_priv_reg_fault_state()
9295 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_bad_op_fault_state()
/linux/drivers/gpu/drm/radeon/
H A Dcikd.h1358 #define CP_ME1_PIPE0_INT_CNTL 0xC214 macro
H A Dcik.c6868 WREG32(CP_ME1_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
7051 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7222 WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0); in cik_irq_set()