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Searched refs:CP_INT_CNTL_RING0 (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c1891 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, in gfx_v12_0_enable_gui_idle_interrupt()
1893 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, in gfx_v12_0_enable_gui_idle_interrupt()
1895 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, in gfx_v12_0_enable_gui_idle_interrupt()
1897 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, in gfx_v12_0_enable_gui_idle_interrupt()
4712 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_gfx_eop_interrupt_state()
4714 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_gfx_eop_interrupt_state()
4720 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_gfx_eop_interrupt_state()
4722 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_gfx_eop_interrupt_state()
4882 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_priv_reg_fault_state()
4928 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_bad_op_fault_state()
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H A Dgfx_v11_0.c2232 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, in gfx_v11_0_enable_gui_idle_interrupt()
2234 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, in gfx_v11_0_enable_gui_idle_interrupt()
2236 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, in gfx_v11_0_enable_gui_idle_interrupt()
2238 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, in gfx_v11_0_enable_gui_idle_interrupt()
6340 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state()
6342 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state()
6348 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state()
6350 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state()
6516 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_priv_reg_fault_state()
6562 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_bad_op_fault_state()
[all …]
H A Dgfx_v10_0.c5434 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, in gfx_v10_0_enable_gui_idle_interrupt()
5436 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, in gfx_v10_0_enable_gui_idle_interrupt()
5438 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, in gfx_v10_0_enable_gui_idle_interrupt()
5440 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, in gfx_v10_0_enable_gui_idle_interrupt()
9068 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
9074 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
9235 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_priv_reg_fault_state()
9281 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_bad_op_fault_state()
9326 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_priv_inst_fault_state()
/linux/drivers/gpu/drm/radeon/
H A Dsi.c5128 u32 tmp = RREG32(CP_INT_CNTL_RING0); in si_enable_gui_idle_interrupt()
5136 WREG32(CP_INT_CNTL_RING0, tmp); in si_enable_gui_idle_interrupt()
5933 tmp = RREG32(CP_INT_CNTL_RING0) & in si_disable_interrupt_state()
5935 WREG32(CP_INT_CNTL_RING0, tmp); in si_disable_interrupt_state()
6051 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in si_irq_set()
6083 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in si_irq_set()
H A Dsid.h1276 #define CP_INT_CNTL_RING0 0xC1A8 macro
H A Dcik.c5760 u32 tmp = RREG32(CP_INT_CNTL_RING0); in cik_enable_gui_idle_interrupt()
5766 WREG32(CP_INT_CNTL_RING0, tmp); in cik_enable_gui_idle_interrupt()
6859 tmp = RREG32(CP_INT_CNTL_RING0) & in cik_disable_interrupt_state()
6861 WREG32(CP_INT_CNTL_RING0, tmp); in cik_disable_interrupt_state()
7037 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in cik_irq_set()
7217 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()
H A Dcikd.h1331 #define CP_INT_CNTL_RING0 0xC1A8 macro