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Searched refs:CLK_AUDDIV_0 (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt8196-topckgen.c84 #define CLK_AUDDIV_0 0x020c macro
921 CLK_AUDDIV_0, 16, 1, CLK_AUDDIV_2, 0, 8, CLK_AUDDIV_0, 0),
923 CLK_AUDDIV_0, 17, 1, CLK_AUDDIV_2, 8, 8, CLK_AUDDIV_0, 1),
925 CLK_AUDDIV_0, 18, 1, CLK_AUDDIV_2, 16, 8, CLK_AUDDIV_0, 2),
927 CLK_AUDDIV_0, 19, 1, CLK_AUDDIV_2, 24, 8, CLK_AUDDIV_0, 3),
930 CLK_AUDDIV_0, 20, 1, CLK_AUDDIV_3, 0, 8, CLK_AUDDIV_0, 4),
932 CLK_AUDDIV_0, 21, 1, CLK_AUDDIV_3, 8, 8, CLK_AUDDIV_0, 5),
934 CLK_AUDDIV_0, 22, 1, CLK_AUDDIV_3, 16, 8, CLK_AUDDIV_0, 6),
936 CLK_AUDDIV_0, 23, 1, CLK_AUDDIV_3, 24, 8, CLK_AUDDIV_0, 7),
939 CLK_AUDDIV_0, 24, 1, CLK_AUDDIV_4, 0, 8, CLK_AUDDIV_0, 8),
[all …]
/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-afe-clk.c423 .div_pdn_reg = CLK_AUDDIV_0,
429 .div_apll_sel_reg = CLK_AUDDIV_0,
436 .div_pdn_reg = CLK_AUDDIV_0,
442 .div_apll_sel_reg = CLK_AUDDIV_0,
449 .div_pdn_reg = CLK_AUDDIV_0,
455 .div_apll_sel_reg = CLK_AUDDIV_0,
462 .div_pdn_reg = CLK_AUDDIV_0,
468 .div_apll_sel_reg = CLK_AUDDIV_0,
475 .div_pdn_reg = CLK_AUDDIV_0,
481 .div_apll_sel_reg = CLK_AUDDIV_0,
[all …]
H A Dmt8192-afe-clk.h32 #define CLK_AUDDIV_0 0x0320 macro
/linux/sound/soc/mediatek/mt6797/
H A Dmt6797-reg.h183 #define CLK_AUDDIV_0 0x05a0 macro