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Searched refs:BLC_PWM_CTL2 (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/gma500/
H A Doaktrail_device.c69 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); in oaktrail_set_brightness()
100 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); in oaktrail_backlight_init()
179 regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2); in oaktrail_save_display_registers()
303 PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2); in oaktrail_restore_display_registers()
H A Dcdv_device.c72 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; in cdv_backlight_combination_mode()
257 regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2); in cdv_save_display_registers()
329 REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2); in cdv_restore_display_registers()
H A Dcdv_intel_lvds.c638 pwm = REG_READ(BLC_PWM_CTL2); in cdv_intel_lvds_init()
644 REG_WRITE(BLC_PWM_CTL2, pwm); in cdv_intel_lvds_init()
H A Dpsb_intel_reg.h81 #define BLC_PWM_CTL2 0x61250 macro
H A Dcdv_intel_dp.c2024 pwm_ctrl = REG_READ(BLC_PWM_CTL2); in cdv_intel_dp_init()
2026 REG_WRITE(BLC_PWM_CTL2, pwm_ctrl); in cdv_intel_dp_init()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_backlight_regs.h24 #define BLC_PWM_CTL2 _MMIO(0x61250) /* 965+ only */ macro
H A Dintel_backlight.c392 intel_de_rmw(display, BLC_PWM_CTL2, BLM_PWM_ENABLE, 0); in i965_disable_backlight()
620 ctl2 = intel_de_read(display, BLC_PWM_CTL2); in i965_enable_backlight()
626 intel_de_write(display, BLC_PWM_CTL2, ctl2); in i965_enable_backlight()
641 intel_de_write(display, BLC_PWM_CTL2, ctl2); in i965_enable_backlight()
642 intel_de_posting_read(display, BLC_PWM_CTL2); in i965_enable_backlight()
643 intel_de_write(display, BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); in i965_enable_backlight()
1369 ctl2 = intel_de_read(display, BLC_PWM_CTL2); in i965_setup_backlight()