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Searched refs:BIT_ULL (Results 1 – 25 of 637) sorted by relevance

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/linux/drivers/gpu/drm/panfrost/
H A Dpanfrost_issues.h142 BIT_ULL(HW_ISSUE_9435))
145 BIT_ULL(HW_ISSUE_6367) | \
146 BIT_ULL(HW_ISSUE_6787) | \
147 BIT_ULL(HW_ISSUE_8408) | \
148 BIT_ULL(HW_ISSUE_9510) | \
149 BIT_ULL(HW_ISSUE_10649) | \
150 BIT_ULL(HW_ISSUE_10676) | \
151 BIT_ULL(HW_ISSUE_10883) | \
152 BIT_ULL(HW_ISSUE_11020) | \
153 BIT_ULL(HW_ISSUE_11035) | \
[all …]
H A Dpanfrost_features.h29 BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \
30 BIT_ULL(HW_FEATURE_V4))
37 BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
38 BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
39 BIT_ULL(HW_FEATURE_XAFFINITY) | \
40 BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT))
51 BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
52 BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
53 BIT_ULL(HW_FEATURE_XAFFINITY) | \
54 BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \
[all …]
/linux/arch/mips/include/asm/
H A Dcpu.h359 #define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */
360 #define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */
361 #define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
362 #define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
363 #define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
364 #define MIPS_CPU_32FPR BIT_ULL( 6) /* 32 dbl. prec. FP registers */
365 #define MIPS_CPU_COUNTER BIT_ULL( 7) /* Cycle count/compare */
366 #define MIPS_CPU_WATCH BIT_ULL( 8) /* watchpoint registers */
367 #define MIPS_CPU_DIVEC BIT_ULL( 9) /* dedicated interrupt vector */
368 #define MIPS_CPU_VCE BIT_ULL(10) /* virt. coherence conflict possible */
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/linux/drivers/ras/amd/atl/
H A Ddehash.c20 intlv_bit = !!(BIT_ULL(intlv_bit_pos) & ctx->ret_addr); in df2_dehash_addr()
23 hashed_bit ^= FIELD_GET(BIT_ULL(12), ctx->ret_addr); in df2_dehash_addr()
24 hashed_bit ^= FIELD_GET(BIT_ULL(18), ctx->ret_addr); in df2_dehash_addr()
25 hashed_bit ^= FIELD_GET(BIT_ULL(21), ctx->ret_addr); in df2_dehash_addr()
26 hashed_bit ^= FIELD_GET(BIT_ULL(30), ctx->ret_addr); in df2_dehash_addr()
29 ctx->ret_addr ^= BIT_ULL(intlv_bit_pos); in df2_dehash_addr()
44 intlv_bit = !!(BIT_ULL(intlv_bit_pos) & ctx->ret_addr); in df3_dehash_addr()
47 hashed_bit ^= FIELD_GET(BIT_ULL(14), ctx->ret_addr); in df3_dehash_addr()
48 hashed_bit ^= FIELD_GET(BIT_ULL(18), ctx->ret_addr) & hash_ctl_64k; in df3_dehash_addr()
49 hashed_bit ^= FIELD_GET(BIT_ULL(23), ctx->ret_addr) & hash_ctl_2M; in df3_dehash_addr()
[all …]
/linux/drivers/mmc/host/
H A Dcavium.h120 #define MIO_EMM_DMA_FIFO_CFG_CLR BIT_ULL(16)
124 #define MIO_EMM_DMA_FIFO_CMD_RW BIT_ULL(62)
125 #define MIO_EMM_DMA_FIFO_CMD_INTDIS BIT_ULL(60)
126 #define MIO_EMM_DMA_FIFO_CMD_SWAP32 BIT_ULL(59)
127 #define MIO_EMM_DMA_FIFO_CMD_SWAP16 BIT_ULL(58)
128 #define MIO_EMM_DMA_FIFO_CMD_SWAP8 BIT_ULL(57)
129 #define MIO_EMM_DMA_FIFO_CMD_ENDIAN BIT_ULL(56)
132 #define MIO_EMM_CMD_SKIP_BUSY BIT_ULL(62)
134 #define MIO_EMM_CMD_VAL BIT_ULL(59)
135 #define MIO_EMM_CMD_DBUF BIT_ULL(55)
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/linux/drivers/net/ethernet/cavium/thunder/
H A Dthunder_bgx.h36 #define CMR_PKT_TX_EN BIT_ULL(13)
37 #define CMR_PKT_RX_EN BIT_ULL(14)
38 #define CMR_EN BIT_ULL(15)
40 #define CMR_GLOBAL_CFG_FCS_STRIP BIT_ULL(6)
57 #define RX_DMACX_CAM_EN BIT_ULL(48)
87 #define SPU_CTL_LOW_POWER BIT_ULL(11)
88 #define SPU_CTL_LOOPBACK BIT_ULL(14)
89 #define SPU_CTL_RESET BIT_ULL(15)
91 #define SPU_STATUS1_RCV_LNK BIT_ULL(2)
93 #define SPU_STATUS2_RCVFLT BIT_ULL(10)
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/linux/drivers/infiniband/hw/irdma/
H A Ddefs.h173 #define IRDMA_FEATURE_RTS_AE BIT_ULL(0)
174 #define IRDMA_FEATURE_CQ_RESIZE BIT_ULL(1)
175 #define IRDMA_FEATURE_64_BYTE_CQE BIT_ULL(5)
176 #define IRDMA_FEATURE_ATOMIC_OPS BIT_ULL(6)
177 #define IRDMA_FEATURE_SRQ BIT_ULL(7)
178 #define IRDMA_FEATURE_CQE_TIMESTAMPING BIT_ULL(8)
329 #define IRDMA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)
332 #define IRDMA_CQPSQ_QHASH_IPV4VALID BIT_ULL(60)
333 #define IRDMA_CQPSQ_QHASH_VLANVALID BIT_ULL(59)
335 #define IRDMA_CQPSQ_STATS_WQEVALID BIT_ULL(63)
[all …]
H A Duda_d.h17 #define IRDMA_UDA_QPSQ_PUSHWQE BIT_ULL(56)
18 #define IRDMA_UDA_QPSQ_INLINEDATAFLAG BIT_ULL(57)
22 #define IRDMA_UDA_QPSQ_NOCHECKSUM BIT_ULL(45)
23 #define IRDMA_UDA_QPSQ_AHIDXVALID BIT_ULL(46)
24 #define IRDMA_UDA_QPSQ_LOCAL_FENCE BIT_ULL(61)
28 #define IRDMA_UDA_QPSQ_MULTICAST BIT_ULL(63)
39 #define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM BIT_ULL(45)
44 #define IRDMA_UDAQPC_IPV4_M BIT_ULL(3)
45 #define IRDMA_UDAQPC_INSERTVLANTAG BIT_ULL(5)
46 #define IRDMA_UDAQPC_ISQP1 BIT_ULL(6)
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/linux/drivers/iommu/riscv/
H A Diommu-bits.h42 #define RISCV_IOMMU_CAPABILITIES_SV32 BIT_ULL(8)
43 #define RISCV_IOMMU_CAPABILITIES_SV39 BIT_ULL(9)
44 #define RISCV_IOMMU_CAPABILITIES_SV48 BIT_ULL(10)
45 #define RISCV_IOMMU_CAPABILITIES_SV57 BIT_ULL(11)
46 #define RISCV_IOMMU_CAPABILITIES_SVPBMT BIT_ULL(15)
47 #define RISCV_IOMMU_CAPABILITIES_SV32X4 BIT_ULL(16)
48 #define RISCV_IOMMU_CAPABILITIES_SV39X4 BIT_ULL(17)
49 #define RISCV_IOMMU_CAPABILITIES_SV48X4 BIT_ULL(18)
50 #define RISCV_IOMMU_CAPABILITIES_SV57X4 BIT_ULL(19)
51 #define RISCV_IOMMU_CAPABILITIES_AMO_MRIF BIT_ULL(21)
[all …]
/linux/arch/loongarch/include/asm/
H A Dcpu.h130 #define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG)
131 #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM)
132 #define LOONGARCH_CPU_SCQ BIT_ULL(CPU_FEATURE_SCQ)
133 #define LOONGARCH_CPU_UAL BIT_ULL(CPU_FEATURE_UAL)
134 #define LOONGARCH_CPU_FPU BIT_ULL(CPU_FEATURE_FPU)
135 #define LOONGARCH_CPU_LSX BIT_ULL(CPU_FEATURE_LSX)
136 #define LOONGARCH_CPU_LASX BIT_ULL(CPU_FEATURE_LASX)
137 #define LOONGARCH_CPU_CRC32 BIT_ULL(CPU_FEATURE_CRC32)
138 #define LOONGARCH_CPU_COMPLEX BIT_ULL(CPU_FEATURE_COMPLEX)
139 #define LOONGARCH_CPU_CRYPTO BIT_ULL(CPU_FEATURE_CRYPTO)
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_flow.h17 (BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_DA) | \
18 BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA))
20 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
21 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
23 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
24 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA))
26 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PRE32_SA) | \
27 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PRE32_DA))
29 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PRE48_SA) | \
30 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PRE48_DA))
[all …]
/linux/arch/x86/include/asm/
H A Dmce.h13 #define MCG_CTL_P BIT_ULL(8) /* MCG_CTL register available */
14 #define MCG_EXT_P BIT_ULL(9) /* Extended registers available */
15 #define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */
16 #define MCG_SEAM_NR BIT_ULL(12) /* MCG_STATUS_SEAM_NR supported */
20 #define MCG_SER_P BIT_ULL(24) /* MCA recovery/new status bits */
21 #define MCG_ELOG_P BIT_ULL(26) /* Extended error log supported */
22 #define MCG_LMCE_P BIT_ULL(27) /* Local machine check supported */
25 #define MCG_STATUS_RIPV BIT_ULL(0) /* restart ip valid */
26 #define MCG_STATUS_EIPV BIT_ULL(1) /* ip points to correct instruction */
27 #define MCG_STATUS_MCIP BIT_ULL(2) /* machine check in progress */
[all …]
H A Dmsr-index.h100 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
218 #define ARCH_CAP_ITS_NO BIT_ULL(62) /*
293 #define LBR_INFO_MISPRED BIT_ULL(63)
294 #define LBR_INFO_IN_TX BIT_ULL(62)
295 #define LBR_INFO_ABORT BIT_ULL(61)
296 #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60)
329 #define PERF_CAP_PEBS_TRAP BIT_ULL(6)
330 #define PERF_CAP_ARCH_REG BIT_ULL(7)
332 #define PERF_CAP_FW_WRITES BIT_ULL(13)
333 #define PERF_CAP_PEBS_BASELINE BIT_ULL(14)
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/linux/drivers/net/ethernet/broadcom/bnge/
H A Dbnge.h41 BNGE_FW_CAP_SHORT_CMD = BIT_ULL(0),
42 BNGE_FW_CAP_LLDP_AGENT = BIT_ULL(1),
43 BNGE_FW_CAP_DCBX_AGENT = BIT_ULL(2),
44 BNGE_FW_CAP_IF_CHANGE = BIT_ULL(3),
45 BNGE_FW_CAP_KONG_MB_CHNL = BIT_ULL(4),
46 BNGE_FW_CAP_ERROR_RECOVERY = BIT_ULL(5),
47 BNGE_FW_CAP_PKG_VER = BIT_ULL(6),
48 BNGE_FW_CAP_CFA_ADV_FLOW = BIT_ULL(7),
49 BNGE_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 = BIT_ULL(8),
50 BNGE_FW_CAP_PCIE_STATS_SUPPORTED = BIT_ULL(9),
[all …]
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.h790 #define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
791 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
792 BIT_ULL(MTK_CLK_TRGPLL))
793 #define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
794 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
795 BIT_ULL(MTK_CLK_GP2) | \
796 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
797 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
798 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
799 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
[all …]
/linux/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_dev.h16 #define KOMEDA_EVENT_VSYNC BIT_ULL(0)
17 #define KOMEDA_EVENT_FLIP BIT_ULL(1)
18 #define KOMEDA_EVENT_URUN BIT_ULL(2)
19 #define KOMEDA_EVENT_IBSY BIT_ULL(3)
20 #define KOMEDA_EVENT_OVR BIT_ULL(4)
21 #define KOMEDA_EVENT_EOW BIT_ULL(5)
22 #define KOMEDA_EVENT_MODE BIT_ULL(6)
23 #define KOMEDA_EVENT_FULL BIT_ULL(7)
24 #define KOMEDA_EVENT_EMPTY BIT_ULL(8)
26 #define KOMEDA_ERR_TETO BIT_ULL(14)
[all …]
/linux/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_regs_cn9k.h20 #define CN93_VF_RING_OFFSET BIT_ULL(17)
69 #define CN93_VF_R_IN_CTL_IDLE BIT_ULL(28)
71 #define CN93_VF_R_IN_CTL_IS_64B BIT_ULL(24)
72 #define CN93_VF_R_IN_CTL_D_NSR BIT_ULL(8)
73 #define CN93_VF_R_IN_CTL_D_ESR BIT_ULL(6)
74 #define CN93_VF_R_IN_CTL_D_ROR BIT_ULL(5)
75 #define CN93_VF_R_IN_CTL_NSR BIT_ULL(3)
76 #define CN93_VF_R_IN_CTL_ESR BIT_ULL(1)
77 #define CN93_VF_R_IN_CTL_ROR BIT_ULL(0)
120 #define CN93_VF_R_OUT_INT_LEVELS_BMODE BIT_ULL(63)
[all …]
/linux/drivers/vdpa/pds/
H A Ddebugfs.c54 u64 mask = BIT_ULL(i); in print_feature_bits_all()
57 case BIT_ULL(VIRTIO_NET_F_CSUM): in print_feature_bits_all()
60 case BIT_ULL(VIRTIO_NET_F_GUEST_CSUM): in print_feature_bits_all()
63 case BIT_ULL(VIRTIO_NET_F_CTRL_GUEST_OFFLOADS): in print_feature_bits_all()
66 case BIT_ULL(VIRTIO_NET_F_MTU): in print_feature_bits_all()
69 case BIT_ULL(VIRTIO_NET_F_MAC): in print_feature_bits_all()
72 case BIT_ULL(VIRTIO_NET_F_GUEST_TSO4): in print_feature_bits_all()
75 case BIT_ULL(VIRTIO_NET_F_GUEST_TSO6): in print_feature_bits_all()
78 case BIT_ULL(VIRTIO_NET_F_GUEST_ECN): in print_feature_bits_all()
81 case BIT_ULL(VIRTIO_NET_F_GUEST_UFO): in print_feature_bits_all()
[all …]
/linux/drivers/firmware/efi/
H A Dcper-x86.c11 #define VALID_LAPIC_ID BIT_ULL(0)
12 #define VALID_CPUID_INFO BIT_ULL(1)
29 #define INFO_VALID_CHECK_INFO BIT_ULL(0)
30 #define INFO_VALID_TARGET_ID BIT_ULL(1)
31 #define INFO_VALID_REQUESTOR_ID BIT_ULL(2)
32 #define INFO_VALID_RESPONDER_ID BIT_ULL(3)
33 #define INFO_VALID_IP BIT_ULL(4)
35 #define CHECK_VALID_TRANS_TYPE BIT_ULL(0)
36 #define CHECK_VALID_OPERATION BIT_ULL(1)
37 #define CHECK_VALID_LEVEL BIT_ULL(2)
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drpm.h21 #define RPM_NIX0_RESET BIT_ULL(3)
22 #define RPMX_RX_TS_PREPEND BIT_ULL(22)
23 #define RPMX_TX_PTP_1S_SUPPORT BIT_ULL(17)
30 #define RPMX_MTI_PCS_LBK BIT_ULL(14)
36 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE BIT_ULL(29)
37 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE BIT_ULL(28)
38 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE BIT_ULL(8)
39 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE BIT_ULL(19)
57 #define RPMX_CMR_RX_OVR_BP_EN(x) BIT_ULL((x) + 8)
58 #define RPMX_CMR_RX_OVR_BP_BP(x) BIT_ULL((x) + 4)
[all …]
H A Dcgx.h29 #define DATA_PKT_TX_EN BIT_ULL(53)
30 #define DATA_PKT_RX_EN BIT_ULL(54)
34 #define FW_CGX_INT BIT_ULL(1)
36 #define CGX_NIX0_RESET BIT_ULL(2)
37 #define CGX_NIX1_RESET BIT_ULL(3)
38 #define CGX_NSCI_DROP BIT_ULL(9)
45 #define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3)
46 #define CGX_DMAC_CAM_ACCEPT BIT_ULL(3)
47 #define CGX_DMAC_MCAST_MODE_CAM BIT_ULL(2)
48 #define CGX_DMAC_MCAST_MODE BIT_ULL(1)
[all …]
/linux/tools/arch/x86/include/asm/
H A Dmsr-index.h100 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
218 #define ARCH_CAP_ITS_NO BIT_ULL(62) /*
293 #define LBR_INFO_MISPRED BIT_ULL(63)
294 #define LBR_INFO_IN_TX BIT_ULL(62)
295 #define LBR_INFO_ABORT BIT_ULL(61)
296 #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60)
329 #define PERF_CAP_PEBS_TRAP BIT_ULL(6)
330 #define PERF_CAP_ARCH_REG BIT_ULL(7)
332 #define PERF_CAP_FW_WRITES BIT_ULL(13)
333 #define PERF_CAP_PEBS_BASELINE BIT_ULL(14)
[all …]
/linux/tools/testing/selftests/kvm/include/x86/
H A Dpmu.h31 #define ARCH_PERFMON_EVENTSEL_USR BIT_ULL(16)
32 #define ARCH_PERFMON_EVENTSEL_OS BIT_ULL(17)
33 #define ARCH_PERFMON_EVENTSEL_EDGE BIT_ULL(18)
34 #define ARCH_PERFMON_EVENTSEL_PIN_CONTROL BIT_ULL(19)
35 #define ARCH_PERFMON_EVENTSEL_INT BIT_ULL(20)
36 #define ARCH_PERFMON_EVENTSEL_ANY BIT_ULL(21)
37 #define ARCH_PERFMON_EVENTSEL_ENABLE BIT_ULL(22)
38 #define ARCH_PERFMON_EVENTSEL_INV BIT_ULL(23)
42 #define INTEL_RDPMC_METRICS BIT_ULL(29)
43 #define INTEL_RDPMC_FIXED BIT_ULL(30)
[all …]
/linux/drivers/net/ethernet/intel/iavf/
H A Diavf.h303 #define IAVF_FLAG_AQ_ENABLE_QUEUES BIT_ULL(0)
304 #define IAVF_FLAG_AQ_DISABLE_QUEUES BIT_ULL(1)
305 #define IAVF_FLAG_AQ_ADD_MAC_FILTER BIT_ULL(2)
306 #define IAVF_FLAG_AQ_ADD_VLAN_FILTER BIT_ULL(3)
307 #define IAVF_FLAG_AQ_DEL_MAC_FILTER BIT_ULL(4)
308 #define IAVF_FLAG_AQ_DEL_VLAN_FILTER BIT_ULL(5)
309 #define IAVF_FLAG_AQ_CONFIGURE_QUEUES BIT_ULL(6)
310 #define IAVF_FLAG_AQ_MAP_VECTORS BIT_ULL(7)
311 #define IAVF_FLAG_AQ_HANDLE_RESET BIT_ULL(8)
312 #define IAVF_FLAG_AQ_CONFIGURE_RSS BIT_ULL(9) /* direct AQ config */
[all …]
/linux/include/media/
H A Drc-map.h15 #define RC_PROTO_BIT_UNKNOWN BIT_ULL(RC_PROTO_UNKNOWN)
16 #define RC_PROTO_BIT_OTHER BIT_ULL(RC_PROTO_OTHER)
17 #define RC_PROTO_BIT_RC5 BIT_ULL(RC_PROTO_RC5)
18 #define RC_PROTO_BIT_RC5X_20 BIT_ULL(RC_PROTO_RC5X_20)
19 #define RC_PROTO_BIT_RC5_SZ BIT_ULL(RC_PROTO_RC5_SZ)
20 #define RC_PROTO_BIT_JVC BIT_ULL(RC_PROTO_JVC)
21 #define RC_PROTO_BIT_SONY12 BIT_ULL(RC_PROTO_SONY12)
22 #define RC_PROTO_BIT_SONY15 BIT_ULL(RC_PROTO_SONY15)
23 #define RC_PROTO_BIT_SONY20 BIT_ULL(RC_PROTO_SONY20)
24 #define RC_PROTO_BIT_NEC BIT_ULL(RC_PROTO_NEC)
[all …]

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