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Searched refs:BIT (Results 1 – 25 of 5411) sorted by relevance

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/linux/drivers/platform/x86/intel/pmc/
H A Dmtl.c30 {"PMC", BIT(0)},
31 {"OPI", BIT(1)},
32 {"SPI", BIT(2)},
33 {"XHCI", BIT(3)},
34 {"SPA", BIT(4)},
35 {"SPB", BIT(5)},
36 {"SPC", BIT(6)},
37 {"GBE", BIT(7)},
39 {"SATA", BIT(0)},
40 {"DSP0", BIT(
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H A Dptl.c14 {"PMC_0", BIT(0)},
15 {"FUSE_OSSE", BIT(1)},
16 {"ESPISPI", BIT(2)},
17 {"XHCI", BIT(3)},
18 {"SPA", BIT(4)},
19 {"SPB", BIT(5)},
20 {"MPFPW2", BIT(6)},
21 {"GBE", BIT(7)},
23 {"SBR16B20", BIT(0)},
24 {"SBR8B20", BIT(
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H A Darl.c63 {"AON2_OFF_STS", BIT(0)},
64 {"AON3_OFF_STS", BIT(1)},
65 {"AON4_OFF_STS", BIT(2)},
66 {"AON5_OFF_STS", BIT(3)},
67 {"AON1_OFF_STS", BIT(4)},
68 {"XTAL_LVM_OFF_STS", BIT(5)},
69 {"AON3_SPL_OFF_STS", BIT(9)},
70 {"DMI3FPW_0_PLL_OFF_STS", BIT(10)},
71 {"DMI3FPW_1_PLL_OFF_STS", BIT(11)},
72 {"G5X16FPW_0_PLL_OFF_STS", BIT(1
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H A Dadl.c15 {"SPI/eSPI", BIT(2)},
16 {"XHCI", BIT(3)},
17 {"SPA", BIT(4)},
18 {"SPB", BIT(5)},
19 {"SPC", BIT(6)},
20 {"GBE", BIT(7)},
22 {"SATA", BIT(0)},
23 {"HDA_PGD0", BIT(1)},
24 {"HDA_PGD1", BIT(2)},
25 {"HDA_PGD2", BIT(
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H A Dcnp.c18 {"PMC", BIT(0)},
19 {"OPI-DMI", BIT(1)},
20 {"SPI/eSPI", BIT(2)},
21 {"XHCI", BIT(3)},
22 {"SPA", BIT(4)},
23 {"SPB", BIT(5)},
24 {"SPC", BIT(6)},
25 {"GBE", BIT(7)},
27 {"SATA", BIT(0)},
28 {"HDA_PGD0", BIT(
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H A Dtgl.c22 {"PSF9", BIT(0)},
23 {"RES_66", BIT(1)},
24 {"RES_67", BIT(2)},
25 {"RES_68", BIT(3)},
26 {"RES_69", BIT(4)},
27 {"RES_70", BIT(5)},
28 {"TBTLSX", BIT(6)},
43 {"USB2PLL_OFF_STS", BIT(18)},
44 {"PCIe/USB3.1_Gen2PLL_OFF_STS", BIT(19)},
45 {"PCIe_Gen3PLL_OFF_STS", BIT(2
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/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen4_ras.h11 #define ADF_GEN4_ERRSOU0_BIT BIT(0)
18 #define ADF_GEN4_ERRSOU1_HIAEUNCERRLOG_CPP0_BIT BIT(0)
19 #define ADF_GEN4_ERRSOU1_HICPPAGENTCMDPARERRLOG_BIT BIT(1)
20 #define ADF_GEN4_ERRSOU1_RIMEM_PARERR_STS_BIT BIT(2)
21 #define ADF_GEN4_ERRSOU1_TIMEM_PARERR_STS_BIT BIT(3)
22 #define ADF_GEN4_ERRSOU1_RIMISCSTS_BIT BIT(4)
51 * BIT(0) - BIT(3) - ri_iosf_pdata_rxq[0:3] parity error
52 * BIT(4) - ri_tlq_phdr parity error
53 * BIT(
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H A Dadf_gen6_ras.h23 #define ADF_GEN6_ERRSOU0_MASK BIT(0)
25 #define ADF_GEN6_ERRSOU1_CPP0_MEUNC_BIT BIT(0)
26 #define ADF_GEN6_ERRSOU1_CPP_CMDPARERR_BIT BIT(1)
27 #define ADF_GEN6_ERRSOU1_RIMEM_PARERR_STS_BIT BIT(2)
28 #define ADF_GEN6_ERRSOU1_TIMEM_PARERR_STS_BIT BIT(3)
29 #define ADF_GEN6_ERRSOU1_SFICMD_PARERR_BIT BIT(4)
38 #define ADF_GEN6_ERRMSK1_CPP0_MEUNC_BIT BIT(0)
39 #define ADF_GEN6_ERRMSK1_CPP_CMDPARERR_BIT BIT(1)
40 #define ADF_GEN6_ERRMSK1_RIMEM_PARERR_STS_BIT BIT(2)
41 #define ADF_GEN6_ERRMSK1_TIMEM_PARERR_STS_BIT BIT(
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/linux/drivers/clk/stm32/
H A Dstm32mp13_rcc.h238 #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0)
241 #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0)
244 #define RCC_MP_APRSTCR_RDCTLEN BIT(0)
257 #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
258 #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
261 #define RCC_BR_RSTSCLRR_PORRSTF BIT(0)
262 #define RCC_BR_RSTSCLRR_BORRSTF BIT(1)
263 #define RCC_BR_RSTSCLRR_PADRSTF BIT(2)
264 #define RCC_BR_RSTSCLRR_HCSSRSTF BIT(3)
265 #define RCC_BR_RSTSCLRR_VCORERSTF BIT(
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/linux/include/linux/soc/mediatek/
H A Dinfracfg.h8 #define MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 BIT(1)
9 #define MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 BIT(2)
10 #define MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S BIT(6)
11 #define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 BIT(10)
12 #define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1 BIT(11)
13 #define MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB BIT(13)
14 #define MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB BIT(14)
15 #define MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 BIT(21)
16 #define MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG BIT(22)
20 #define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP BIT(
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/linux/drivers/gpu/drm/bridge/
H A Dsil-sii8620.h35 #define BIT_SYS_CTRL1_OTPVMUTEOVR_SET BIT(7)
36 #define BIT_SYS_CTRL1_VSYNCPIN BIT(6)
37 #define BIT_SYS_CTRL1_OTPADROPOVR_SET BIT(5)
38 #define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD BIT(4)
39 #define BIT_SYS_CTRL1_OTP2XVOVR_EN BIT(3)
40 #define BIT_SYS_CTRL1_OTP2XAOVR_EN BIT(2)
41 #define BIT_SYS_CTRL1_TX_CTRL_HDMI BIT(1)
42 #define BIT_SYS_CTRL1_OTPAMUTEOVR_SET BIT(0)
46 #define BIT_DPD_PWRON_PLL BIT(7)
47 #define BIT_DPD_PDNTX12 BIT(
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/linux/drivers/net/ethernet/freescale/dpaa2/
H A Ddpkg.h64 #define NH_FLD_ETH_DA BIT(0)
65 #define NH_FLD_ETH_SA BIT(1)
66 #define NH_FLD_ETH_LENGTH BIT(2)
67 #define NH_FLD_ETH_TYPE BIT(3)
68 #define NH_FLD_ETH_FINAL_CKSUM BIT(4)
69 #define NH_FLD_ETH_PADDING BIT(5)
70 #define NH_FLD_ETH_ALL_FIELDS (BIT(6) - 1)
73 #define NH_FLD_VLAN_VPRI BIT(0)
74 #define NH_FLD_VLAN_CFI BIT(1)
75 #define NH_FLD_VLAN_VID BIT(
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/linux/drivers/net/wireless/realtek/rtw89/
H A Dreg.h9 #define B_AX_AUTOLOAD_SUS BIT(5)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(8)
18 #define B_AX_FEN_BB_GLB_RSTN BIT(1)
19 #define B_AX_FEN_BBRSTB BIT(0)
22 #define B_AX_SOP_ASWRM BIT(31)
23 #define B_AX_SOP_PWMM_DSWR BIT(29)
24 #define B_AX_SOP_EDSWR BIT(28)
25 #define B_AX_XTAL_OFF_A_DIE BIT(2
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/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A Dregs.h10 #define SYS_ISO_MD2PP BIT(0)
11 #define SYS_ISO_ANALOG_IPS BIT(5)
12 #define SYS_ISO_DIOR BIT(9)
13 #define SYS_ISO_PWC_EV25V BIT(14)
14 #define SYS_ISO_PWC_EV12V BIT(15)
17 #define SYS_FUNC_BBRSTB BIT(0)
18 #define SYS_FUNC_BB_GLB_RSTN BIT(1)
19 #define SYS_FUNC_USBA BIT(2)
20 #define SYS_FUNC_UPLL BIT(3)
21 #define SYS_FUNC_USBD BIT(
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/linux/sound/soc/codecs/
H A Dsma1307.h234 #define SMA1307_POWER_MASK BIT(0)
236 #define SMA1307_POWER_ON BIT(0)
239 #define SMA1307_RESET_MASK BIT(1)
240 #define SMA1307_RESET_ON BIT(1)
243 #define SMA1307_LEFTPOL_MASK BIT(3)
245 #define SMA1307_HIGH_FIRST_CH BIT(3)
248 #define SMA1307_SCK_RISING_MASK BIT(2)
250 #define SMA1307_SCK_RISING_EDGE BIT(2)
253 #define SMA1307_SPK_MUTE_MASK BIT(0)
255 #define SMA1307_SPK_MUTE BIT(
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H A Dmt6357.h16 #define MT6357_GPIO8_DIR_MASK BIT(8)
18 #define MT6357_GPIO8_DIR_OUTPUT BIT(8)
19 #define MT6357_GPIO9_DIR_MASK BIT(9)
21 #define MT6357_GPIO9_DIR_OUTPUT BIT(9)
22 #define MT6357_GPIO10_DIR_MASK BIT(10)
24 #define MT6357_GPIO10_DIR_OUTPUT BIT(10)
25 #define MT6357_GPIO11_DIR_MASK BIT(11)
27 #define MT6357_GPIO11_DIR_OUTPUT BIT(11)
28 #define MT6357_GPIO12_DIR_MASK BIT(12)
30 #define MT6357_GPIO12_DIR_OUTPUT BIT(1
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/linux/drivers/gpu/drm/mcde/
H A Dmcde_dsi_regs.h8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
9 #define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE BIT(1)
10 #define DSI_MCTL_MAIN_DATA_CTL_VID_EN BIT(2)
11 #define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL BIT(3)
12 #define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL BIT(4)
13 #define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN BIT(5)
14 #define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN BIT(6)
15 #define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN BIT(7)
16 #define DSI_MCTL_MAIN_DATA_CTL_READ_EN BIT(8)
17 #define DSI_MCTL_MAIN_DATA_CTL_BTA_EN BIT(
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/linux/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h171 #define QCA956X_MAC_CFG1_SOFT_RST BIT(31)
172 #define QCA956X_MAC_CFG1_RX_RST BIT(19)
173 #define QCA956X_MAC_CFG1_TX_RST BIT(18)
174 #define QCA956X_MAC_CFG1_LOOPBACK BIT(8)
175 #define QCA956X_MAC_CFG1_RX_EN BIT(2)
176 #define QCA956X_MAC_CFG1_TX_EN BIT(0)
179 #define QCA956X_MAC_CFG2_IF_1000 BIT(9)
180 #define QCA956X_MAC_CFG2_IF_10_100 BIT(8)
181 #define QCA956X_MAC_CFG2_HUGE_FRAME_EN BIT(5)
182 #define QCA956X_MAC_CFG2_LEN_CHECK BIT(
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/linux/drivers/staging/sm750fb/
H A Dddk750_reg.h7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
25 #define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY BIT(2
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/linux/drivers/usb/dwc2/
H A Dhw.h14 #define GOTGCTL_EUSB2_DISC_SUPP BIT(28)
15 #define GOTGCTL_CHIRPEN BIT(27)
18 #define GOTGCTL_CURMODE_HOST BIT(21)
19 #define GOTGCTL_OTGVER BIT(20)
20 #define GOTGCTL_BSESVLD BIT(19)
21 #define GOTGCTL_ASESVLD BIT(18)
22 #define GOTGCTL_DBNC_SHORT BIT(17)
23 #define GOTGCTL_CONID_B BIT(16)
24 #define GOTGCTL_DBNCE_FLTR_BYPASS BIT(15)
25 #define GOTGCTL_DEVHNPEN BIT(1
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/linux/drivers/net/dsa/microchip/
H A Dksz9477_reg.h43 #define SW_GIGABIT_ABLE BIT(6)
44 #define SW_REDUNDANCY_ABLE BIT(5)
45 #define SW_AVB_ABLE BIT(4)
63 #define SW_QW_ABLE BIT(5)
69 #define LUE_INT BIT(31)
70 #define TRIG_TS_INT BIT(30)
71 #define APB_TIMEOUT_INT BIT(29)
82 #define SW_SPARE_REG_2 BIT(7)
83 #define SW_SPARE_REG_1 BIT(6)
84 #define SW_SPARE_REG_0 BIT(
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/linux/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/
H A Dsun8i_a83t_mipi_csi2_reg.h14 #define SUN8I_A83T_MIPI_CSI2_CTRL_RESET_N BIT(31)
24 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_ECC_ERR_DBL BIT(28)
25 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_CKSM_ERR_VC3 BIT(27)
26 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_CKSM_ERR_VC2 BIT(26)
27 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_CKSM_ERR_VC1 BIT(25)
28 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_CKSM_ERR_VC0 BIT(24)
29 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_SEQ_ERR_DT3 BIT(23)
30 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_SEQ_ERR_DT2 BIT(22)
31 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_SEQ_ERR_DT1 BIT(21)
32 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_SEQ_ERR_DT0 BIT(2
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/linux/include/linux/mfd/
H A Dtps6594.h249 #define TPS6594_BIT_BUCK_EN BIT(0)
250 #define TPS6594_BIT_BUCK_FPWM BIT(1)
251 #define TPS6594_BIT_BUCK_FPWM_MP BIT(2)
252 #define TPS6594_BIT_BUCK_VSEL BIT(3)
253 #define TPS6594_BIT_BUCK_VMON_EN BIT(4)
254 #define TPS6594_BIT_BUCK_PLDN BIT(5)
255 #define TPS6594_BIT_BUCK_RV_SEL BIT(7)
279 #define TPS6594_BIT_LDO_EN BIT(0)
280 #define TPS6594_BIT_LDO_SLOW_RAMP BIT(1)
281 #define TPS6594_BIT_LDO_VMON_EN BIT(
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/linux/drivers/comedi/drivers/
H A Dni_stc.h25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
29 #define NISTC_INTA_ACK_AI_START BIT(11)
30 #define NISTC_INTA_ACK_AI_START2 BIT(10)
31 #define NISTC_INTA_ACK_AI_START1 BIT(9)
32 #define NISTC_INTA_ACK_AI_SC_TC BIT(8)
33 #define NISTC_INTA_ACK_AI_SC_TC_ERR BIT(7)
34 #define NISTC_INTA_ACK_G0_TC_ERR BIT(
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/linux/include/linux/mfd/abx500/
H A Dab8500-sysctrl.h83 #define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
84 #define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)
85 #define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)
86 #define AB8500_TURNONSTATUS_RTCALARM BIT(3)
87 #define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
88 #define AB8500_TURNONSTATUS_VBUSDET BIT(5)
89 #define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)
91 #define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)
92 #define AB8500_RESETSTATUS_SWRESETN4500NSTATUS BIT(2)
97 #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ1STATUS BIT(
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