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/linux/tools/testing/selftests/bpf/prog_tests/
H A Dcgroup_attach_override.c8 #define BAR "/foo/bar/" macro
55 bar = test__join_cgroup(BAR); in serial_test_cgroup_attach_override()
66 "attach prog to %s failed, errno=%d\n", BAR, errno)) in serial_test_cgroup_attach_override()
74 "detach prog from %s failed, errno=%d\n", BAR, errno)) in serial_test_cgroup_attach_override()
84 "attach prog to %s failed, errno=%d\n", BAR, errno)) in serial_test_cgroup_attach_override()
98 "attach prog to %s failed, errno=%d\n", BAR, errno)) in serial_test_cgroup_attach_override()
103 "attach prog to %s unexpectedly succeeded\n", BAR)) in serial_test_cgroup_attach_override()
108 "detach prog from %s failed, errno=%d\n", BAR, errno)) in serial_test_cgroup_attach_override()
123 "attach prog to %s unexpectedly succeeded\n", BAR)) in serial_test_cgroup_attach_override()
129 "attach prog to %s unexpectedly succeeded\n", BAR)) in serial_test_cgroup_attach_override()
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/linux/Documentation/arch/powerpc/
H A Dpci_iov_resource_on_powernv.rst172 discover the BAR sizes and assign addresses for them. For VF devices,
173 software uses VF BAR registers in the *PF* SR-IOV Capability to
177 When a VF BAR in the PF SR-IOV Capability is programmed, it sets the
180 1MB VF BAR0, the address in that VF BAR sets the base of an 8MB region.
182 is a BAR0 for one of the VFs. Note that even though the VF BAR
195 the segment size matches the smallest VF BAR, which means larger VF
210 and different segment sizes. If we have VFs that each have a 1MB BAR
211 and a 32MB BAR, we could use one M64 window to assign 1MB segments and
215 more in the next two sections. For a given VF BAR, we need to
216 effectively reserve the entire 256 segments (256 * VF BAR siz
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H A Deeh-pci-error-recovery.rst95 config space (the base address registers (BAR's), latency timer,
177 It saves the device BAR's and then calls rpaphp_unconfig_pci_adapter().
183 It then resets the PCI card, reconfigures the device BAR's, and
/linux/Documentation/gpu/rfc/
H A Di915_small_bar.rst2 I915 Small BAR RFC Section
4 Starting from DG2 we will have resizable BAR support for device local-memory(i.e
5 I915_MEMORY_CLASS_DEVICE), but in some cases the final BAR size might still be
14 underneath the device has a small BAR, meaning only some portion of it is CPU
41 1) Error capture is best effort on small BAR systems; if the pages are not
/linux/Documentation/accel/amdxdna/
H A Damdnpu.rst89 * PSP BAR: Expose the AMD PSP (Platform Security Processor) function
90 * SMU BAR: Expose the AMD SMU (System Management Unit) function
91 * SRAM BAR: Expose ring buffers for the mailbox
92 * Mailbox BAR: Expose the mailbox control registers (head, tail and ISR
94 * Public Register BAR: Expose public registers
96 On specific devices, the above-mentioned BAR type might be combined into a
97 single physical PCIe BAR. Or a module might require two physical PCIe BARs to
100 * On AMD Phoenix device, PSP, SMU, Public Register BARs are on PCIe BAR index 0.
101 * On AMD Strix Point device, Mailbox and Public Register BARs are on PCIe BAR
102 index 0. The PSP has some registers in PCIe BAR inde
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/linux/drivers/ntb/hw/idt/
H A DKconfig21 accepted by a BAR. Note that BAR0 must map PCI configuration space
25 BAR settings of peer NT-functions, the BAR setups can't be done over
/linux/Documentation/misc-devices/
H A Dpci-endpoint-test.rst15 #) verifying addresses programmed in BAR
31 Tests the BAR. The number of the BAR to be tested
/linux/Documentation/PCI/endpoint/
H A Dpci-ntb-function.rst117 the outbound ATU such that transactions to Doorbell BAR will be routed
128 will configure the outbound ATU such that transactions to MW BAR
155 same BAR. The initial portion of the region will have doorbell
166 same BAR. The initial portion of the region will have config region
177 Used to determine the offset within the DB BAR that should be written
233 If one 32-bit BAR is allocated for each of these regions, the scheme would
237 BAR NO CONSTRUCTS USED
247 However if we allocate a separate BAR for each of the regions, there would not
259 BAR NO CONSTRUCTS USED
H A Dpci-vntb-function.rst106 BAR NO CONSTRUCTS USED
119 BAR NO CONSTRUCTS USED
/linux/Documentation/kbuild/
H A Dkconfig-language.rst128 bool "foo" if BAR
129 default y if BAR
133 depends on BAR
151 if FOO depends on BAR that is not set.
177 depends on BAR
182 FOO BAR BAZ's default choice for BAZ
198 FOO should imply not only BAZ, but also its dependency BAR::
202 imply BAR
527 depends on BAR && m
578 depends on BAR || !BA
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/linux/Documentation/translations/zh_CN/PCI/
H A Dacpi-info.rst29 ACPI资源描述是通过ACPI命名空间中设备的_CRS对象完成的[2]。_CRS就像一个通用的PCI BAR：
H A Dpci.rst
/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-pxa-pci-ce4100.txt21 offset from be base of the BAR (which would be
23 the same BAR)
/linux/Documentation/translations/zh_CN/userspace-api/accelerators/
H A Docxl.rst
/linux/drivers/pci/endpoint/
H A DKconfig37 dedicated BAR, which the EP maps to the controller's message address.
/linux/drivers/firmware/broadcom/
H A DKconfig21 a PCI BAR.
/linux/Documentation/networking/device_drivers/ethernet/huawei/
H A Dhinic3.rst47 hinic3_csr.h Register definitions in the BAR
48 hinic3_hwif.[ch] Interface for BAR
/linux/Documentation/driver-api/driver-model/
H A Ddevres.rst394 pcim_iomap() : do iomap() on a single BAR
396 pcim_iomap_table() : array of mapped addresses indexed by BAR
397 pcim_iounmap() : do iounmap() on a single BAR
/linux/Documentation/accel/qaic/
H A Daic100.rst46 * The first BAR is 4K in size, and exposes the MHI interface to the host.
48 * The second BAR is 2M in size, and exposes the DMA Bridge interface to the
51 * The third BAR is variable in size based on an individual AIC100's
52 configuration, but defaults to 64K. This BAR currently has no purpose.
265 DBC registers are exposed to the host via the second BAR. Each DBC consumes
266 4KB of space in the BAR.
/linux/Documentation/driver-api/
H A Dmen-chameleon-bus.rst67 header lists the device id, PCI BAR, offset from the beginning of the PCI
68 BAR, size in the FPGA, interrupt number and some other properties currently
H A Dswitchtec.rst97 NT EP BAR 2 will be dynamically configured as a Direct Window, and
/linux/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/
H A Dswitchdev.rst79 A subfunction has a dedicated window in PCI BAR space that is not shared
82 PCI BAR space.
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-pci486 These files provide an interface to PCIe Resizable BAR support.
487 A file is created for each BAR resource (N) supported by the
488 PCIe Resizable BAR extended capability of the device. Reading
494 The bitmap represents supported resource sizes for the BAR,
496 example the device supports 64MB, 128MB, and 256MB BAR sizes.
/linux/Documentation/scsi/
H A DChangeLog.sym53c8xx37 - Get both the BAR cookies used by CPU and actual PCI BAR
40 BAR values to destination address to make decision.
44 PCI BAR value from the BAR cookie is now useless.
/linux/Documentation/gpu/nova/core/
H A Dvbios.rst7 images in the ROM of the GPU. The VBIOS is mirrored onto the BAR 0 space and is read

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