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Searched refs:AON_RESET (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/clk/qcom/
H A Dgdsc.h65 #define AON_RESET BIT(4) macro
H A Dgpucc-sdm845.c139 .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
H A Dgpucc-sm8150.c241 .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
H A Dgpucc-sm8250.c249 .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
H A Dgpucc-sdm660.c254 .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
H A Dgpucc-msm8998.c270 .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
H A Dgpucc-qcm2290.c317 .flags = CLAMP_IO | AON_RESET | SW_RESET,
H A Dgpucc-sm6375.c380 .flags = CLAMP_IO | SW_RESET | AON_RESET,
H A Dgpucc-sar2130p.c417 .flags = CLAMP_IO | AON_RESET | SW_RESET,
H A Dgpucc-sm8350.c528 .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
H A Dgpucc-sa8775p.c585 .flags = AON_RESET | RETAIN_FF_ENABLE,
H A Dgpucc-sm8650.c565 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
H A Dgpucc-x1e80100.c557 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
H A Dgdsc.c274 if (sc->flags & AON_RESET) in gdsc_enable()
H A Dgpucc-sm4450.c694 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
H A Dgpucc-sm8450.c692 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,