1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Samsung's Exynos USI (Universal Serial Interface) 8 9maintainers: 10 - Sam Protsenko <semen.protsenko@linaro.org> 11 - Krzysztof Kozlowski <krzk@kernel.org> 12 13description: | 14 The USI IP-core provides configurable support for serial protocols, enabling 15 different serial communication modes depending on the version. 16 17 In USIv1, configurations are available to enable either one or two protocols 18 simultaneously in select combinations - High-Speed I2C0, High-Speed 19 I2C1, SPI, UART, High-Speed I2C0 and I2C1 or both High-Speed 20 I2C1 and UART. 21 22 In USIv2, only one protocol can be active at a time, either UART, SPI, or 23 High-Speed I2C. 24 25 The USI core shares internal circuits across protocols, meaning only the 26 selected configuration is active at any given time. USI is modeled as a node 27 with zero or more child nodes, each representing a serial sub-node device. The 28 mode setting selects which particular function will be used. 29 30properties: 31 $nodename: 32 pattern: "^usi@[0-9a-f]+$" 33 34 compatible: 35 oneOf: 36 - items: 37 - enum: 38 - google,gs101-usi 39 - samsung,exynosautov9-usi 40 - samsung,exynosautov920-usi 41 - const: samsung,exynos850-usi 42 - enum: 43 - samsung,exynos850-usi 44 - samsung,exynos8895-usi 45 46 reg: 47 maxItems: 1 48 49 clocks: 50 maxItems: 2 51 52 clock-names: 53 items: 54 - const: pclk 55 - const: ipclk 56 57 ranges: true 58 59 "#address-cells": 60 const: 1 61 62 "#size-cells": 63 const: 1 64 65 samsung,sysreg: 66 $ref: /schemas/types.yaml#/definitions/phandle-array 67 items: 68 - items: 69 - description: phandle to System Register syscon node 70 - description: offset of SW_CONF register for this USI controller 71 description: 72 Should be phandle/offset pair. The phandle to System Register syscon node 73 (for the same domain where this USI controller resides) and the offset 74 of SW_CONF register for this USI controller. 75 76 samsung,mode: 77 $ref: /schemas/types.yaml#/definitions/uint32 78 enum: [0, 1, 2, 3, 4, 5, 6] 79 description: 80 Selects USI function (which serial protocol to use). Refer to 81 <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values. 82 83 samsung,clkreq-on: 84 type: boolean 85 description: 86 Enable this property if underlying protocol requires the clock to be 87 continuously provided without automatic gating. As suggested by SoC 88 manual, it should be set in case of SPI/I2C slave, UART Rx and I2C 89 multi-master mode. Usually this property is needed if USI mode is set 90 to "UART". 91 92 This property is optional. 93 94patternProperties: 95 "^i2c@[0-9a-f]+$": 96 $ref: /schemas/i2c/i2c-exynos5.yaml 97 description: Child node describing underlying I2C 98 99 "^serial@[0-9a-f]+$": 100 $ref: /schemas/serial/samsung_uart.yaml 101 description: Child node describing underlying UART/serial 102 103 "^spi@[0-9a-f]+$": 104 $ref: /schemas/spi/samsung,spi.yaml 105 description: Child node describing underlying SPI 106 107required: 108 - compatible 109 - ranges 110 - "#address-cells" 111 - "#size-cells" 112 - samsung,sysreg 113 - samsung,mode 114 115allOf: 116 - if: 117 properties: 118 compatible: 119 contains: 120 enum: 121 - samsung,exynos850-usi 122 123 then: 124 properties: 125 reg: 126 maxItems: 1 127 128 clocks: 129 items: 130 - description: Bus (APB) clock 131 - description: Operating clock for UART/SPI/I2C protocol 132 133 clock-names: 134 maxItems: 2 135 136 samsung,mode: 137 enum: [0, 1, 2, 3] 138 139 required: 140 - reg 141 - clocks 142 - clock-names 143 144 - if: 145 properties: 146 compatible: 147 contains: 148 enum: 149 - samsung,exynos8895-usi 150 151 then: 152 properties: 153 reg: false 154 155 clocks: 156 items: 157 - description: Bus (APB) clock 158 - description: Operating clock for UART/SPI protocol 159 160 clock-names: 161 maxItems: 2 162 163 samsung,clkreq-on: false 164 165 required: 166 - clocks 167 - clock-names 168 169additionalProperties: false 170 171examples: 172 - | 173 #include <dt-bindings/interrupt-controller/arm-gic.h> 174 #include <dt-bindings/soc/samsung,exynos-usi.h> 175 176 usi0: usi@138200c0 { 177 compatible = "samsung,exynos850-usi"; 178 reg = <0x138200c0 0x20>; 179 samsung,sysreg = <&sysreg_peri 0x1010>; 180 samsung,mode = <USI_MODE_UART>; 181 samsung,clkreq-on; /* needed for UART mode */ 182 #address-cells = <1>; 183 #size-cells = <1>; 184 ranges; 185 clocks = <&cmu_peri 32>, <&cmu_peri 31>; 186 clock-names = "pclk", "ipclk"; 187 188 serial_0: serial@13820000 { 189 compatible = "samsung,exynos850-uart"; 190 reg = <0x13820000 0xc0>; 191 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 192 clocks = <&cmu_peri 32>, <&cmu_peri 31>; 193 clock-names = "uart", "clk_uart_baud0"; 194 }; 195 196 hsi2c_0: i2c@13820000 { 197 compatible = "samsung,exynos850-hsi2c", "samsung,exynosautov9-hsi2c"; 198 reg = <0x13820000 0xc0>; 199 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 200 #address-cells = <1>; 201 #size-cells = <0>; 202 clocks = <&cmu_peri 31>, <&cmu_peri 32>; 203 clock-names = "hsi2c", "hsi2c_pclk"; 204 status = "disabled"; 205 }; 206 }; 207