| /linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
| H A D | memory.json | 31 "BriefDescription": "Counts all code reads that were supplied by DRAM.",
37 "PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: 0",
42 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
48 "PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: 0",
53 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
59 "PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: 0",
64 "BriefDescription": "Counts all code reads that were supplied by DRAM.",
70 "PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: 0",
75 "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
81 "PublicDescription": "Counts modified writebacks from L1 cache and L2 cache that were no
[all...] |
| H A D | cache.json | 279 "BriefDescription": "Counts the number of memory uops retired that were splits.",
285 "PublicDescription": "Counts the number of memory uops retired that were splits. Available PDIST counters: 0",
312 "BriefDescription": "Counts all code reads that were supplied by the L3 cache.",
318 "PublicDescription": "Counts all code reads that were supplied by the L3 cache. Available PDIST counters: 0",
323 "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
329 "PublicDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. Available PDIST counters: 0",
334 "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
340 "PublicDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. Available PDIST counters: 0",
345 "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
351 "PublicDescription": "Counts all code reads that were supplie
[all...] |
| H A D | pipeline.json | 307 "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
311 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
316 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.",
324 "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
332 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.",
349 "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.",
356 "BriefDescription": "Counts the number of issue slots every cycle that were no
[all...] |
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/ |
| H A D | retired.json | 32 "PublicDescription": "Counts branches counted by BR_RETIRED which were mispredicted and caused a pipeline flush."
40 "PublicDescription": "Counts architecturally executed indirect branches excluding procedure returns that were taken."
44 "PublicDescription": "Counts architecturally executed direct branches that were correctly predicted."
48 "PublicDescription": "Counts architecturally executed direct branches that were mispredicted and caused a pipeline flush."
52 "PublicDescription": "Counts architecturally executed indirect branches including procedure returns that were correctly predicted."
56 "PublicDescription": "Counts architecturally executed indirect branches including procedure returns that were mispredicted and caused a pipeline flush."
60 "PublicDescription": "Counts architecturally executed procedure returns that were correctly predicted."
64 "PublicDescription": "Counts architecturally executed procedure returns that were mispredicted and caused a pipeline flush."
68 "PublicDescription": "Counts architecturally executed indirect branches excluding procedure returns that were correctly predicted."
72 "PublicDescription": "Counts architecturally executed indirect branches excluding procedure returns that were mispredicte
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/alderlaken/ |
| H A D | memory.json | 60 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
66 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: 0",
71 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
77 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache. Available PDIST counters: 0",
82 "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
88 "PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0",
93 "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
99 "PublicDescription": "Counts demand data reads that were not supplied by the L3 cache. Available PDIST counters: 0",
104 "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]",
110 "PublicDescription": "Counts demand data reads that were no
[all...] |
| H A D | adln-metrics.json | 74 "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions",
82 "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls",
89 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count",
93 "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear",
100 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
104 "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend",
109 "PublicDescription": "Counts the number of issue slots that were no
[all...] |
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/ |
| H A D | retired.json | 36 "PublicDescription": "Counts branches counted by BR_RETIRED which were mispredicted and caused a pipeline flush."
44 "PublicDescription": "Counts architecturally executed direct branches that were taken."
48 "PublicDescription": "Counts architecturally executed indirect branches excluding procedure returns that were taken."
52 "PublicDescription": "Counts architecturally executed direct branches that were correctly predicted."
56 "PublicDescription": "Counts architecturally executed direct branches that were mispredicted and caused a pipeline flush."
60 "PublicDescription": "Counts architecturally executed indirect branches including procedure returns that were correctly predicted."
64 "PublicDescription": "Counts architecturally executed indirect branches including procedure returns that were mispredicted and caused a pipeline flush."
68 "PublicDescription": "Counts architecturally executed procedure returns that were correctly predicted."
72 "PublicDescription": "Counts architecturally executed procedure returns that were mispredicted and caused a pipeline flush."
76 "PublicDescription": "Counts architecturally executed indirect branches excluding procedure returns that were correctl
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | memory.json | 180 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
186 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: 0",
191 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.",
197 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST counters: 0",
202 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
208 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster. Available PDIST counters: 0",
213 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
219 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode. Available PDIST counters: 0",
224 "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
230 "PublicDescription": "Counts demand data reads that were supplie
[all...] |
| H A D | cache.json | 119 "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES] Available PDIST counters: 0",
128 "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS] Available PDIST counters: 0",
146 "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once. Available PDIST counters: 0",
218 "PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once. Available PDIST counters: 0",
236 "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS] Available PDIST counters: 0",
245 "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL] Available PDIST counters: 0",
402 "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
407 "PublicDescription": "Counts retired load instructions whose data sources were Hit
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | memory.json | 180 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
186 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: 0",
191 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.",
197 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST counters: 0",
202 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
208 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster. Available PDIST counters: 0",
213 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
219 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode. Available PDIST counters: 0",
224 "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
230 "PublicDescription": "Counts demand data reads that were supplie
[all...] |
| H A D | cache.json | 119 "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES] Available PDIST counters: 0",
128 "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS] Available PDIST counters: 0",
146 "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once. Available PDIST counters: 0",
218 "PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once. Available PDIST counters: 0",
236 "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS] Available PDIST counters: 0",
245 "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL] Available PDIST counters: 0",
402 "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
407 "PublicDescription": "Counts retired load instructions whose data sources were Hit
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/icelakex/ |
| H A D | memory.json | 117 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
127 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.",
137 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
147 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
157 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
167 "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
177 "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.",
187 "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
197 "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
207 "BriefDescription": "Counts demand data reads that were supplie
[all...] |
| H A D | cache.json | 374 "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
379 "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.",
404 "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
409 "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
414 "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
419 "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",
424 "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
429 "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.",
583 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.",
603 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snoope
[all...] |
| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | hist-v4l2.rst | 29 aliases ``O_NONCAP`` and ``O_NOIO`` were defined. Applications can set
40 struct ``video_standard`` and the color subcarrier fields were
59 module. The ``YUV422`` and ``YUV411`` planar image formats were added.
62 output devices were added.
110 Version 0.20 introduced a number of changes which were *not backward
115 1. Some typos in ``V4L2_FMT_FLAG`` symbols were fixed. struct v4l2_clip
137 4. All the different get- and set-format commands were swept into one
152 ``VIDIOC_S_PARM`` ioctls were merged with ``VIDIOC_G_OUTPARM`` and
159 6. Control enumeration was simplified, and two new control flags were
188 cause errors if it were bein
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/elkhartlake/ |
| H A D | pipeline.json | 307 "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
311 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
316 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.",
324 "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
332 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.",
349 "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.",
356 "BriefDescription": "Counts the number of issue slots every cycle that were no
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/arrowlake/ |
| H A D | frontend.json | 56 "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
62 "BriefDescription": "Counts the number of instructions retired that were tagged with having preceded with frontend bound behavior",
70 "BriefDescription": "Counts the number of instructions retired that were tagged with having preceded with frontend bound behavior",
138 "BriefDescription": "Counts the number of instructions retired that were tagged following an ms flow due to the bubble/wasted issue slot from exiting long ms flow",
142 "PublicDescription": "Counts the number of instructions retired that were tagged following an ms flow due to the bubble/wasted issue slot from exiting long ms flow",
148 "BriefDescription": "Counts the number of instructions retired that were tagged following an ms flow due to the bubble/wasted issue slot from exiting long ms flow",
152 "PublicDescription": "Counts the number of instructions retired that were tagged following an ms flow due to the bubble/wasted issue slot from exiting long ms flow",
158 "BriefDescription": "Counts the number of instructions retired that were tagged every cycle the decoder is unable to send 4 uops",
167 "BriefDescription": "Counts the number of instructions retired that were tagged every cycle the decoder is unable to send 3 uops per cycle.",
182 "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were expose
[all...] |
| /linux/Documentation/networking/device_drivers/ethernet/altera/ |
| H A D | altera_tse.rst | 14 driver were built for a Cyclone(R) V SOC FPGA board, a Cyclone(R) V FPGA board,
26 Quartus toolchain. Quartus 13.1 and 14.0 were used to build the design that
201 statistic is a count of the number of packets received that were not addressed
205 statistic is a count of the number of packets received that were addressed to
209 statistic is a count of the number of packets received that were addressed to
218 statistic counts the number of packets transmitted that were not addressed to
222 statistic counts the number of packets transmitted that were addressed to a
226 statistic counts the number of packets transmitted that were addressed to a
250 This statistic counts the total number of packets received that were 64 octets
254 2819. This statistic counts the total number of packets received that were
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/pantherlake/ |
| H A D | memory.json | 144 "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
150 "PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0",
156 "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
162 "PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0",
168 "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
174 "PublicDescription": "Counts demand data reads that were not supplied by the L3 cache. Available PDIST counters: 0",
180 "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
186 "PublicDescription": "Counts demand data reads that were not supplied by the L3 cache. Available PDIST counters: 0",
192 "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
198 "PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were no
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
| H A D | frontend.json | 12 "BriefDescription": "Counts the number of instructions retired that were tagged with having preceded with frontend bound behavior",
35 "BriefDescription": "Counts the number of instructions retired that were tagged following an ms flow due to the bubble/wasted issue slot from exiting long ms flow",
39 "PublicDescription": "Counts the number of instructions retired that were tagged following an ms flow due to the bubble/wasted issue slot from exiting long ms flow",
44 "BriefDescription": "Counts the number of instructions retired that were tagged every cycle the decoder is unable to send 3 uops per cycle.",
52 "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to icache miss",
60 "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss",
|
| H A D | memory.json | 76 "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
82 "PublicDescription": "Counts demand data reads that were not supplied by the L3 cache. Available PDIST counters: 0",
87 "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket.",
93 "PublicDescription": "Counts demand data reads that were supplied by DRAM attached to this socket. Available PDIST counters: 0",
98 "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.",
104 "PublicDescription": "Counts demand data reads that were supplied by DRAM attached to another socket. Available PDIST counters: 0",
109 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
115 "PublicDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0",
|
| /linux/tools/perf/pmu-events/arch/x86/meteorlake/ |
| H A D | memory.json | 302 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
308 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: 0",
314 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
320 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache. Available PDIST counters: 0",
326 "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
332 "PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0",
338 "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
344 "PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0",
350 "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
356 "PublicDescription": "Counts demand data reads that were no
[all...] |
| /linux/Documentation/scheduler/ |
| H A D | sched-nice-design.rst | 8 Nice levels were always pretty weak under Linux and people continuously
14 units were driven by the HZ tick, so the smallest timeslice was 1/HZ.
17 much stronger than they were before in 2.4 (and people were happy about
48 this was long ago when hardware was weaker and caches were smaller, and
49 people were running number crunching apps at nice +19.)
83 nice levels were not 'punchy enough', so lots of people had to resort to
104 levels were changed to be "multiplicative" (or exponential) - that way
|
| /linux/tools/perf/pmu-events/arch/x86/grandridge/ |
| H A D | grr-metrics.json | 235 "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions",
243 "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls",
249 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count",
253 "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear",
259 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
263 "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend",
268 "PublicDescription": "Counts the number of issue slots that were no
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/alderlake/ |
| H A D | cache.json | 140 "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES] Available PDIST counters: 0",
170 "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS] Available PDIST counters: 0",
190 "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once. Available PDIST counters: 0",
260 "PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once. Available PDIST counters: 0",
280 "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS] Available PDIST counters: 0",
290 "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL] Available PDIST counters: 0",
561 "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
566 "PublicDescription": "Counts retired load instructions whose data sources were Hit
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| H A D | virtual-memory.json | 7 "PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 1GB pages. The page walks can end with or without a page fault.",
16 "PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.",
25 "PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages. The page walks can end with or without a page fault.",
43 "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault.",
52 "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.",
61 "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.",
97 "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault.",
106 "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.",
115 "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.",
|