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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_2_cleaner_shader.asm31 // Waves are "wave64" and have 128 VGPRs each, which uses all 512 VGPRs per SIMD
32 // Waves in the workgroup share the 64KB of LDS
33 // Each wave clears SGPRs 0 - 95. Because there are 4 waves/SIMD, this is physical SGPRs 0-3…
36 // The shader starts with "S_BARRIER" to ensure SPI has launched all waves of the workgroup
39 // Launches a workgroup with 24 waves per workgroup, yielding 6 waves per SIMD in each CU
40 // Waves are allocating 96 SGPRs
41 // CP sets up SPI_RESOURCE_RESERVE_* registers to prevent these waves from allocating SGPR…
42 // As such, these 6 waves per SIMD are allocated physical SGPRs 224-799
43 // Barriers do not work for >16 waves per workgroup, so we cannot start with S_BARRIER
44 // Instead, the shader starts with an S_SETHALT 1. Once all waves are launched CP will sen…
H A Dgfx_v9_4_3_cleaner_shader.asm31 // Waves are "wave64" and have 128 VGPRs each, which uses all 512 VGPRs per SIMD
32 // Waves in the workgroup share the 64KB of LDS
33 // Each wave clears SGPRs 0 - 95. Because there are 4 waves/SIMD, this is physical SGPRs 0-3…
36 // The shader starts with "S_BARRIER" to ensure SPI has launched all waves of the workgroup
39 // Launches a workgroup with 24 waves per workgroup, yielding 6 waves per SIMD in each CU
40 // Waves are allocating 96 SGPRs
41 // CP sets up SPI_RESOURCE_RESERVE_* registers to prevent these waves from allocating SGPR…
42 // As such, these 6 waves per SIMD are allocated physical SGPRs 224-799
43 // Barriers do not work for >16 waves per workgroup, so we cannot start with S_BARRIER
44 // Instead, the shader starts with an S_SETHALT 1. Once all waves are launched CP will sen…
H A Dgfx_v10_3_0_cleaner_shader.asm28 // Launch 32 waves per CU (16 per SIMD) as a workgroup (threadgroup) to fill every wave slot
29 // Waves are "wave32" and have 64 VGPRs each, which uses all 1024 VGPRs per SIMD
30 // Waves are launched in "CU" mode, and the workgroup shares 64KB of LDS (half of the WGP's LDS)
35 // The shader starts with "S_BARRIER" to ensure SPI has launched all waves of the workgroup
46 // Create 32 waves in a threadgroup (CS waves)
H A Dgfx_v10_1_10_cleaner_shader.asm27 // Launch 32 waves per CU (16 per SIMD) as a workgroup (threadgroup) to fill every wave slot
28 // Waves are "wave32" and have 64 VGPRs each, which uses all 1024 VGPRs per SIMD
29 // Waves are launched in "CU" mode, and the workgroup shares 64KB of LDS (half of the WGP's LDS)
34 // The shader starts with "S_BARRIER" to ensure SPI has launched all waves of the workgroup
44 // Create 32 waves in a threadgroup (CS waves)
H A Dgfx_v11_0_3_cleaner_shader.asm28 // Launch 32 waves per CU (16 per SIMD) as a workgroup (threadgroup) to fill every wave slot
29 // Waves are "wave32" and have 64 VGPRs each, which uses all 1024 VGPRs per SIMD
30 // Waves are launched in "CU" mode, and the workgroup shares 64KB of LDS (half of the WGP's LDS)
35 // The shader starts with "S_BARRIER" to ensure SPI has launched all waves of the workgroup
H A Damdgpu_amdkfd_gfx_v9.c659 * After wavefront launch has been stalled, allocated waves must drain from
660 * SPI in order for debug trap settings to take effect on those waves.
941 * get_wave_count: Read device registers to get number of waves in flight for
959 * parameters to read out waves in flight. Get VMID if there are in get_wave_count()
960 * non-zero waves in flight. in get_wave_count()
979 * shader engine and aggregates the number of waves that are in flight for the
981 * or more queues running and submitting waves to compute units.
983 * @adev: Handle of device from which to get number of waves in flight
986 * @max_waves_per_cu: Output parameter updated with maximum number of waves
998 * The registers that provide the waves in flight are:
[all …]
H A Dgfx_v9_4_2.c214 * make sure that waves of dispatch 0 are all dispacthed to all simds
215 * balanced. both dispatch 0 and dispatch 1 should be halted until all waves
217 * all waves continue.
308 * top hole sgprs. Therefore need 4 waves per SIMD to cover these sgprs
536 wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */ in gfx_v9_4_2_do_sgprs_init()
560 wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */ in gfx_v9_4_2_do_sgprs_init()
564 wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */ in gfx_v9_4_2_do_sgprs_init()
601 wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */ in gfx_v9_4_2_do_sgprs_init()
605 wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */ in gfx_v9_4_2_do_sgprs_init()
H A Damdgpu_amdkfd_gfx_v10.c722 * After wavefront launch has been stalled, allocated waves must drain from
723 * SPI in order for debug trap settings to take effect on those waves.
H A Dgfx_v9_4_3.c3448 * number of gfx waves. Setting 5 bit will make sure gfx only gets in gfx_v9_4_3_emit_wave_limit()
3456 /* Restrict waves for normal/low priority compute queues as well in gfx_v9_4_3_emit_wave_limit()
/linux/Documentation/devicetree/bindings/iio/proximity/
H A Ddevantech-srf04.yaml48 Thus this GPIO is set while the ultrasonic waves are doing one round
/linux/Documentation/devicetree/bindings/pwm/
H A Drenesas,rzg2l-gpt.yaml16 * Up-counting or down-counting (saw waves) or up/down-counting
17 (triangle waves) for each counter.
/linux/sound/soc/intel/catpt/
H A Dpcm.c1091 /* Enable or disable WAVES module */
1092 SOC_SINGLE_BOOL_EXT("Waves Switch", 0,
1094 /* WAVES module parameter control */
1095 SND_SOC_BYTES_TLV("Waves Set Param", 128,
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler_gfx8.asm221 // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for.
226 …s not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get ar…
372 s_barrier //LDS is used? wait for other waves in the same TG
H A Dcwsr_trap_handler_gfx9.asm378 // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for.
383 …s not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get ar…
547 s_barrier //LDS is used? wait for other waves in the same TG
H A Dcwsr_trap_handler_gfx10.asm225 // If ttmp1[30] is set then issue s_barrier to unblock dependent waves.
401 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause
403 // other waves are stuck into the sleep-loop and waiting for wrexec!=0
680 s_barrier //LDS is used? wait for other waves in the same TG
H A Dcwsr_trap_handler_gfx12.asm1004 // initialized with the number of waves in the work group.
1048 // Make barrier and LDS state visible to all waves in the group.
H A Dkfd_process.c255 * kfd_get_cu_occupancy - Collect number of waves in-flight on this device
261 * of waves in flight, etc
/linux/Documentation/gpu/amdgpu/
H A Ddebugfs.rst205 Provides an IOCTL interface used by UMR for interacting with shader waves.
/linux/sound/pci/ac97/
H A Dac97_proc.c75 /* 17 */ "Nvidea/IC Ensemble/KS Waves 3D Stereo Enhancement",
85 /* 27 */ "IC Ensemble/KS Waves",
/linux/drivers/iio/proximity/
H A Dping.c20 * . --> one round trip of ultra sonic waves
H A Dsrf04.c35 * --> one round trip of ultra sonic waves
/linux/drivers/gpu/drm/amd/include/
H A Dkgd_kfd_interface.h211 * guarantee any minimum for the number of waves in-flight. This function
/linux/drivers/net/wireless/ath/ath9k/
H A Dani.c69 * your signal completely if phase is 180 degrees (think of adding sine waves).
/linux/include/uapi/drm/
H A Damdgpu_drm.h99 * execution of all the waves on a device.
/linux/drivers/infiniband/ulp/ipoib/
H A Dipoib_cm.c837 * so don't make waves. in ipoib_cm_handle_tx_wc()

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