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/linux/arch/arm64/boot/dts/apm/
H A Dapm-shadowcat.dtsi132 v2m0: v2m@0 {
133 compatible = "arm,gic-v2m-frame";
137 v2m1: v2m@10000 {
138 compatible = "arm,gic-v2m-frame";
142 v2m2: v2m@20000 {
143 compatible = "arm,gic-v2m-frame";
147 v2m3: v2m@30000 {
148 compatible = "arm,gic-v2m-frame";
152 v2m4: v2m@40000 {
153 compatible = "arm,gic-v2m
[all...]
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2m.dtsi6 * V2M-P1
14 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
18 * CHANGES TO vexpress-v2m-rs1.dtsi!
79 compatible = "arm,vexpress,v2m-p1", "simple-bus";
366 clock-output-names = "v2m:clk24mhz";
373 clock-output-names = "v2m:refclk1mhz";
380 clock-output-names = "v2m:refclk32khz";
387 label = "v2m:green:user1";
393 label = "v2m:green:user2";
399 label = "v2m
[all...]
H A Dvexpress-v2m-rs1.dtsi6 * V2M-P1
14 * original variant (vexpress-v2m.dtsi), but there is a strong
18 * CHANGES TO vexpress-v2m.dtsi!
35 clock-output-names = "v2m:clk24mhz";
42 clock-output-names = "v2m:refclk1mhz";
49 clock-output-names = "v2m:refclk32khz";
56 label = "v2m:green:user1";
62 label = "v2m:green:user2";
68 label = "v2m:green:user3";
74 label = "v2m
[all...]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic.yaml150 "^v2m@[0-9a-f]+$":
155 Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
156 This is enabled by specifying v2m sub-node(s).
160 const: arm,gic-v2m-frame
229 v2m0: v2m@80000 {
230 compatible = "arm,gic-v2m-frame";
237 v2mN: v2m@90000 {
238 compatible = "arm,gic-v2m-frame";
/linux/arch/arm64/boot/dts/broadcom/northstar2/
H A Dns2.dtsi368 v2m0: v2m@0 {
369 compatible = "arm,gic-v2m-frame";
376 v2m1: v2m@10000 {
377 compatible = "arm,gic-v2m-frame";
384 v2m2: v2m@20000 {
385 compatible = "arm,gic-v2m-frame";
392 v2m3: v2m@30000 {
393 compatible = "arm,gic-v2m-frame";
400 v2m4: v2m@40000 {
401 compatible = "arm,gic-v2m
[all...]
/linux/Documentation/devicetree/bindings/soc/renesas/
H A Drenesas,rzv2m-pwc.yaml7 title: Renesas RZ/V2M External Power Sequence Controller (PWC)
10 The PWC IP found in the RZ/V2M family of chips comes with the below
24 - renesas,r9a09g011-pwc # RZ/V2M
H A Drenesas,r9a09g011-sys.yaml7 title: Renesas RZ/V2M System Configuration (SYS)
13 The RZ/V2M-alike SYS (System Configuration) controls the overall
/linux/Documentation/devicetree/bindings/arm/
H A Darm,vexpress-juno.yaml83 V2M-Juno) was introduced as a vehicle for evaluating big.LITTLE on
91 (V2M-Juno r1) was introduced mainly aimed at development of PCIe
100 (V2M-Juno r2). It has the same feature set as Juno r0 and r1. See
154 - arm,vexpress,v2m-p1
178 - arm,vexpress,v2m-p1
181 arm,v2m-memory-map:
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap80x.dtsi110 gic_v2m0: v2m@280000 {
111 compatible = "arm,gic-v2m-frame";
117 gic_v2m1: v2m@290000 {
118 compatible = "arm,gic-v2m-frame";
124 gic_v2m2: v2m@2a0000 {
125 compatible = "arm,gic-v2m-frame";
131 gic_v2m3: v2m@2b0000 {
132 compatible = "arm,gic-v2m-frame";
/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,rzg2l-cpg.yaml7 title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
14 Standby Mode share the same register block. On RZ/V2M, the functionality is
31 - renesas,r9a09g011-cpg # RZ/V2M
/linux/arch/arm64/boot/dts/arm/
H A Drtsm_ve-motherboard-rs2.dtsi5 * "rs2" extension for the v2m motherboard
10 arm,v2m-memory-map = "rs2";
H A Djuno-base.dtsi82 v2m_0: v2m@0 {
83 compatible = "arm,gic-v2m-frame";
88 v2m@10000 {
89 compatible = "arm,gic-v2m-frame";
94 v2m@20000 {
95 compatible = "arm,gic-v2m-frame";
100 v2m@30000 {
101 compatible = "arm,gic-v2m-frame";
/linux/arch/arm/mach-versatile/
H A DMakefile18 obj-$(CONFIG_ARCH_VEXPRESS) := v2m.o
26 obj-$(CONFIG_ARCH_MPS2) += v2m-mps2.o
/linux/Documentation/devicetree/bindings/i2c/
H A Drenesas,rzv2m.yaml7 title: Renesas RZ/V2M I2C Bus Interface
19 - renesas,r9a09g011-i2c # RZ/V2M
/linux/Documentation/devicetree/bindings/usb/
H A Drenesas,usb-xhci.yaml39 - renesas,r9a09g011-xhci # RZ/V2M
41 - const: renesas,rzv2m-xhci # RZ/{V2M, V2MA}
H A Drenesas,rzv2m-usb3drd.yaml7 title: Renesas RZ/V2M USB 3.1 DRD controller
21 - renesas,r9a09g011-usb3drd # RZ/V2M
/linux/drivers/usb/gadget/udc/
H A Drzv2m_usb3drd.c3 * Renesas RZ/V2M USB3DRD driver
135 MODULE_DESCRIPTION("Renesas RZ/V2M USB3DRD driver");
/linux/drivers/soc/renesas/
H A DKconfig381 bool "ARM64 Platform support for R9A09G011 (RZ/V2M)"
387 This enables support for the Renesas RZ/V2M SoC.
445 bool "Renesas RZ/V2M PWC support" if COMPILE_TEST
/linux/drivers/pinctrl/renesas/
H A DKconfig306 bool "pin control support for RZ/V2M" if COMPILE_TEST
313 This selects GPIO and pinctrl driver for Renesas RZ/V2M
/linux/include/dt-bindings/pinctrl/
H A Drzv2m-pinctrl.h3 * This header provides constants for Renesas RZ/V2M pinctrl bindings.
/linux/drivers/usb/host/
H A Dxhci-rzv2m.c3 * xHCI host controller driver for RZ/V2M
/linux/arch/arm64/boot/dts/qcom/
H A Dipq5018.dtsi335 v2m0: v2m@0 {
336 compatible = "arm,gic-v2m-frame";
341 v2m1: v2m@1000 {
342 compatible = "arm,gic-v2m-frame";
/linux/Documentation/hwmon/
H A Dvexpress.rst17 * Section "4.4.14. System Configuration registers" of the V2M-P1 TRM:
/linux/Documentation/devicetree/bindings/serial/
H A Drenesas,em-uart.yaml17 - renesas,r9a09g011-uart # RZ/V2M
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a09g011-v2mevk2.dts3 * Device Tree Source for the RZ/V2M (r9a09g011) Evaluation Kit Board
14 model = "RZ/V2M Evaluation Kit 2.0";

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