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/linux-5.10/drivers/usb/gadget/udc/
Drenesas_usb3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas USB3.0 Peripheral driver (USB gadget)
5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
10 #include <linux/dma-mapping.h>
12 #include <linux/extcon-provider.h>
35 #define USB3_DMA_CH0_CON(n) (0x030 + ((n) - 1) * 0x10) /* n = 1 to 4 */
36 #define USB3_DMA_CH0_PRD_ADR(n) (0x034 + ((n) - 1) * 0x10) /* n = 1 to 4 */
75 #define AXI_INT_PRDEN_CLR_STA_SHIFT(n) (16 + (n) - 1)
76 #define AXI_INT_PRDERR_STA_SHIFT(n) (0 + (n) - 1)
262 * To avoid double-meaning of "0" (xferred 65536 bytes or received zlp if
[all …]
/linux-5.10/drivers/phy/broadcom/
Dphy-bcm-ns-usb3.c1 // SPDX-License-Identifier: GPL-2.0-only
58 int (*phy_write)(struct bcm_ns_usb3 *usb3, u16 reg, u16 value);
63 .compatible = "brcm,ns-ax-usb3-phy",
67 .compatible = "brcm,ns-bx-usb3-phy",
74 static int bcm_ns_usb3_mdio_phy_write(struct bcm_ns_usb3 *usb3, u16 reg, in bcm_ns_usb3_mdio_phy_write() argument
77 return usb3->phy_write(usb3, reg, value); in bcm_ns_usb3_mdio_phy_write()
80 static int bcm_ns_usb3_phy_init_ns_bx(struct bcm_ns_usb3 *usb3) in bcm_ns_usb3_phy_init_ns_bx() argument
84 /* USB3 PLL Block */ in bcm_ns_usb3_phy_init_ns_bx()
85 err = bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, in bcm_ns_usb3_phy_init_ns_bx()
87 if (err < 0) in bcm_ns_usb3_phy_init_ns_bx()
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/linux-5.10/Documentation/devicetree/bindings/phy/
Drenesas,usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
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Dsocionext,uniphier-usb3hs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-usb3-hsphy
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Dnvidia,tegra124-xusb-padctl.txt11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
34 --------------------
35 - compatible: Must be:
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Dqcom,qmp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Manu Gautam <mgautam@codeaurora.org>
20 - qcom,ipq8074-qmp-pcie-phy
21 - qcom,ipq8074-qmp-usb3-phy
22 - qcom,msm8996-qmp-pcie-phy
23 - qcom,msm8996-qmp-ufs-phy
24 - qcom,msm8996-qmp-usb3-phy
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Dti-phy.txt6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
11 e.g. USB3 PHY and SATA PHY on OMAP5.
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
20 - reg-names: "otghs_control" for control-phy-otghs
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/linux-5.10/drivers/usb/cdns3/
DKconfig2 tristate "Cadence USB3 Dual-Role Controller"
4 select USB_XHCI_PLATFORM if USB_XHCI_HCD
7 Say Y here if your system has a Cadence USB3 dual-role controller.
8 It supports: dual-role switch, Host-only, and Peripheral-only.
10 If you choose to build this driver is a dynamically linked
13 if USB_CDNS3
16 bool "Cadence USB3 device controller"
20 Cadence USBSS-DEV driver.
26 bool "Cadence USB3 host controller"
36 tristate "Cadence USB3 support on PCIe-based platforms"
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/linux-5.10/drivers/phy/tegra/
Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
158 if (!usb2) in tegra186_usb2_lane_probe()
159 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
161 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
162 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
163 usb2->base.index = index; in tegra186_usb2_lane_probe()
164 usb2->base.pad = pad; in tegra186_usb2_lane_probe()
165 usb2->base.np = np; in tegra186_usb2_lane_probe()
[all …]
Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
44 if (phy == NULL) in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
[all …]
/linux-5.10/drivers/usb/host/
Dxhci-rcar.c1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver for R-Car SoCs
17 #include "xhci-plat.h"
18 #include "xhci-rcar.h"
21 * - The V3 firmware is for almost all R-Car Gen3 (except r8a7795 ES1.x)
22 * - The V2 firmware is for r8a7795 ES1.x.
23 * - The V2 firmware is possible to use on R-Car Gen2. However, the V2 causes
24 * performance degradation. So, this driver continues to use the V1 if R-Car
26 * - The V1 firmware is impossible to use on R-Car Gen3.
39 #define RCAR_USB3_CONF1 0xa48 /* USB3.0 Configuration1 */
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/linux-5.10/Documentation/devicetree/bindings/usb/
Drenesas,usb3-peri.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/usb/renesas,usb3-peri.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-peri # RZ/G2M
17 - renesas,r8a774b1-usb3-peri # RZ/G2N
18 - renesas,r8a774c0-usb3-peri # RZ/G2E
19 - renesas,r8a774e1-usb3-peri # RZ/G2H
[all …]
Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Neil Armstrong <narmstrong@baylibre.com>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
26 host-only mode.
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Ddwc3.txt3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
10 - clock-names: list of clock names. Ideally should be "ref",
12 - clocks: list of phandle and clock specifier pairs corresponding to
13 entries in the clock-names property.
16 clocks are optional if the parent node (i.e. glue-layer) is compatible to
18 "cavium,octeon-7130-usb-uctl"
20 "samsung,exynos5250-dwusb3"
[all …]
/linux-5.10/fs/ufs/
Dutil.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 return &cpi->c_ubh; in UCPI_UBH()
29 return &spi->s_ubh; in USPI_UBH()
39 struct ufs_super_block_third *usb3) in ufs_get_fs_state() argument
41 switch (UFS_SB(sb)->s_flags & UFS_ST_MASK) { in ufs_get_fs_state()
43 if (fs32_to_cpu(sb, usb3->fs_postblformat) == UFS_42POSTBLFMT) in ufs_get_fs_state()
44 return fs32_to_cpu(sb, usb1->fs_u0.fs_sun.fs_state); in ufs_get_fs_state()
47 return fs32_to_cpu(sb, usb3->fs_un2.fs_sun.fs_state); in ufs_get_fs_state()
49 return fs32_to_cpu(sb, usb1->fs_u1.fs_sunx86.fs_state); in ufs_get_fs_state()
52 return fs32_to_cpu(sb, usb3->fs_un2.fs_44.fs_state); in ufs_get_fs_state()
[all …]
Dsuper.c1 // SPDX-License-Identifier: GPL-2.0-only
16 * Laboratoire MASI - Institut Blaise Pascal
25 * Big-endian to little-endian byte-swapping/bitmaps by
35 * Adrian Rodriguez (adrian@franklins-tower.rutgers.edu)
48 * Francois-Rene Rideau <fare@tunes.org>
52 * on code by Martin von Loewis <martin@mira.isdn.cs.tu-berlin.de>.
84 #include <linux/backing-dev.h>
101 struct ufs_sb_private_info *uspi = UFS_SB(sb)->s_uspi; in ufs_nfs_get_inode()
104 if (ino < UFS_ROOTINO || ino > (u64)uspi->s_ncg * uspi->s_ipg) in ufs_nfs_get_inode()
105 return ERR_PTR(-ESTALE); in ufs_nfs_get_inode()
[all …]
/linux-5.10/arch/arm64/boot/dts/amlogic/
Dmeson-g12b-s922x-khadas-vim3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-g12b-s922x.dtsi"
11 #include "meson-khadas-vim3.dtsi"
12 #include "meson-g12b-khadas-vim3.dtsi"
19 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
21 * an USB3.0 Type A connector and a M.2 Key M slot.
23 * the USB3.0 controller and the PCIe Controller, thus only
25 * If the MCU is configured to mux the PCIe/USB3.0 differential lines
27 * USB3.0 from the USB Complex and enable the PCIe controller.
[all …]
Dmeson-g12b-a311d-khadas-vim3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-g12b-a311d.dtsi"
11 #include "meson-khadas-vim3.dtsi"
12 #include "meson-g12b-khadas-vim3.dtsi"
19 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
21 * an USB3.0 Type A connector and a M.2 Key M slot.
23 * the USB3.0 controller and the PCIe Controller, thus only
25 * If the MCU is configured to mux the PCIe/USB3.0 differential lines
27 * USB3.0 from the USB Complex and enable the PCIe controller.
[all …]
Dmeson-sm1-khadas-vim3l.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "meson-sm1.dtsi"
10 #include "meson-khadas-vim3.dtsi"
11 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
17 vddcpu: regulator-vddcpu {
21 compatible = "pwm-regulator";
23 regulator-name = "VDDCPU";
24 regulator-min-microvolt = <690000>;
25 regulator-max-microvolt = <1050000>;
[all …]
/linux-5.10/drivers/usb/dwc3/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 tristate "DesignWare USB3 DRD Core Support"
6 select USB_XHCI_PLATFORM if USB_XHCI_HCD
7 select USB_ROLE_SWITCH if USB_DWC3_DUAL_ROLE
9 Say Y or M here if your system has a Dual Role SuperSpeed
10 USB controller based on the DesignWare USB3 IP Core.
12 If you choose to build this driver is a dynamically linked
15 if USB_DWC3
21 Select this if you have ULPI type PHY attached to your DWC3
26 default USB_DWC3_DUAL_ROLE if (USB && USB_GADGET)
[all …]
Ddwc3-keystone.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-keystone.c - Keystone Specific Glue layer
5 * Copyright (C) 2010-2013 Texas Instruments Incorporated - https://www.ti.com
7 * Author: WingMan Kwok <w-kwok2@ti.com>
14 #include <linux/dma-mapping.h>
55 val = kdwc3_readl(kdwc->usbss, USBSS_IRQENABLE_SET_0); in kdwc3_enable_irqs()
57 kdwc3_writel(kdwc->usbss, USBSS_IRQENABLE_SET_0, val); in kdwc3_enable_irqs()
64 val = kdwc3_readl(kdwc->usbss, USBSS_IRQENABLE_SET_0); in kdwc3_disable_irqs()
66 kdwc3_writel(kdwc->usbss, USBSS_IRQENABLE_SET_0, val); in kdwc3_disable_irqs()
73 kdwc3_writel(kdwc->usbss, USBSS_IRQENABLE_CLR_0, USBSS_IRQ_COREIRQ_CLR); in dwc3_keystone_interrupt()
[all …]
/linux-5.10/drivers/phy/socionext/
Dphy-uniphier-usb3ss.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-uniphier-usb3ss.c - SS-PHY driver for Socionext UniPhier USB3 controller
4 * Copyright 2015-2018 Socionext Inc.
71 writel(data, priv->base + SSPHY_TESTI); in uniphier_u3ssphy_testio_write()
72 readl(priv->base + SSPHY_TESTO); in uniphier_u3ssphy_testio_write()
73 readl(priv->base + SSPHY_TESTO); in uniphier_u3ssphy_testio_write()
80 u8 field_mask = GENMASK(p->field.msb, p->field.lsb); in uniphier_u3ssphy_set_param()
85 val |= FIELD_PREP(TESTI_ADR_MASK, p->field.reg_no); in uniphier_u3ssphy_set_param()
87 val = readl(priv->base + SSPHY_TESTO); in uniphier_u3ssphy_set_param()
91 data = field_mask & (p->value << p->field.lsb); in uniphier_u3ssphy_set_param()
[all …]
/linux-5.10/drivers/regulator/
Duniphier-regulator.c1 // SPDX-License-Identifier: GPL-2.0
43 struct device *dev = &pdev->dev; in uniphier_regulator_probe()
53 if (!priv) in uniphier_regulator_probe()
54 return -ENOMEM; in uniphier_regulator_probe()
56 priv->data = of_device_get_match_data(dev); in uniphier_regulator_probe()
57 if (WARN_ON(!priv->data)) in uniphier_regulator_probe()
58 return -EINVAL; in uniphier_regulator_probe()
61 if (IS_ERR(base)) in uniphier_regulator_probe()
64 for (i = 0; i < priv->data->nclks; i++) in uniphier_regulator_probe()
65 priv->clk[i].id = priv->data->clock_names[i]; in uniphier_regulator_probe()
[all …]
/linux-5.10/drivers/reset/
Dreset-uniphier-glue.c1 // SPDX-License-Identifier: GPL-2.0
3 // reset-uniphier-glue.c - Glue layer reset driver for UniPhier
12 #include <linux/reset/reset-simple.h>
33 struct device *dev = &pdev->dev; in uniphier_glue_reset_probe()
41 if (!priv) in uniphier_glue_reset_probe()
42 return -ENOMEM; in uniphier_glue_reset_probe()
44 priv->data = of_device_get_match_data(dev); in uniphier_glue_reset_probe()
45 if (WARN_ON(!priv->data || priv->data->nclks > MAX_CLKS || in uniphier_glue_reset_probe()
46 priv->data->nrsts > MAX_RSTS)) in uniphier_glue_reset_probe()
47 return -EINVAL; in uniphier_glue_reset_probe()
[all …]
/linux-5.10/drivers/thunderbolt/
Dtunnel.c1 // SPDX-License-Identifier: GPL-2.0
3 * Thunderbolt driver - Tunneling support
22 /* USB3 adapters use always HopID of 8 for both directions */
40 static const char * const tb_tunnel_names[] = { "PCI", "DP", "DMA", "USB3" };
45 level(__tunnel->tb, "%llx:%x <-> %llx:%x (%s): " fmt, \
46 tb_route(__tunnel->src_port->sw), \
47 __tunnel->src_port->port, \
48 tb_route(__tunnel->dst_port->sw), \
49 __tunnel->dst_port->port, \
50 tb_tunnel_names[__tunnel->type], \
[all …]

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