Searched full:synthesised (Results 1 – 5 of 5) sorted by relevance
45 control the duty cycle for channel x have a second "shadow"/buffer reg synthesised.47 synchronised mode for all channels it has been synthesised for.
9 synthesised into an FPGA or CPLD.
8 synthesised with different options that change the behaviour.
467 * registers have been synthesised. in mchp_core_pwm_probe()
1820 * Instrs Sample(n...) are the synthesised samples occurring in cs_etm__sample()2852 * for samples so that synthesised samples occur from this point in cs_etm__process_event()