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/linux-5.10/arch/arm/boot/dts/
Dstm32f746.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
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Dstm32f429.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
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Dstm32mp151.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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/linux-5.10/Documentation/devicetree/bindings/mfd/
Dst,stm32-timers.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Timers bindings
11 - advanced-control timers consist of a 16-bit auto-reload counter driven
14 - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter
16 - basic timers consist of a 16-bit auto-reload counter driven by a
20 - Benjamin Gaignard <benjamin.gaignard@st.com>
21 - Fabrice Gasnier <fabrice.gasnier@st.com>
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Dst,stm32-lptimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-lptimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Low-Power Timers bindings
10 The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
12 - PWM output (with programmable prescaler, configurable polarity)
13 - Trigger source for STM32 ADC/DAC (LPTIM_OUT)
14 - Several counter modes:
15 - quadrature encoder to detect angular position and direction of rotary
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/linux-5.10/drivers/mfd/
Dstm32-timers.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/mfd/stm32-timers.h>
32 status = dmaengine_tx_status(dma->chan, dma->chan->cookie, &state); in stm32_timers_dma_done()
34 complete(&dma->completion); in stm32_timers_dma_done()
38 * stm32_timers_dma_burst_read - Read from timers registers using DMA.
40 * Read from STM32 timers registers using DMA on a single event.
56 struct regmap *regmap = ddata->regmap; in stm32_timers_dma_burst_read()
57 struct stm32_timers_dma *dma = &ddata->dma; in stm32_timers_dma_burst_read()
69 return -EINVAL; in stm32_timers_dma_burst_read()
73 return -EINVAL; in stm32_timers_dma_burst_read()
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Dstm32-lptimer.c1 // SPDX-License-Identifier: GPL-2.0
3 * STM32 Low-Power Timer parent driver.
6 * Inspired by Benjamin Gaignard's stm32-timers driver
9 #include <linux/mfd/stm32-lptimer.h>
30 * Low-Power Timer supports it. in stm32_lptimer_detect_encoder()
32 ret = regmap_update_bits(ddata->regmap, STM32_LPTIM_CFGR, in stm32_lptimer_detect_encoder()
37 ret = regmap_read(ddata->regmap, STM32_LPTIM_CFGR, &val); in stm32_lptimer_detect_encoder()
41 ret = regmap_update_bits(ddata->regmap, STM32_LPTIM_CFGR, in stm32_lptimer_detect_encoder()
46 ddata->has_encoder = !!(val & STM32_LPTIM_ENC); in stm32_lptimer_detect_encoder()
53 struct device *dev = &pdev->dev; in stm32_lptimer_probe()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 88pm860x-objs := 88pm860x-core.o 88pm860x-i2c.o
7 obj-$(CONFIG_MFD_88PM860X) += 88pm860x.o
8 obj-$(CONFIG_MFD_88PM800) += 88pm800.o 88pm80x.o
9 obj-$(CONFIG_MFD_88PM805) += 88pm805.o 88pm80x.o
10 obj-$(CONFIG_MFD_ACT8945A) += act8945a.o
11 obj-$(CONFIG_MFD_SM501) += sm501.o
12 obj-$(CONFIG_MFD_ASIC3) += asic3.o tmio_core.o
13 obj-$(CONFIG_ARCH_BCM2835) += bcm2835-pm.o
14 obj-$(CONFIG_MFD_BCM590XX) += bcm590xx.o
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
44 tristate "Active-semi ACT8945A"
49 Support for the ACT8945A PMIC from Active-semi. This device
50 features three step-down DC/DC converters and four low-dropout
66 sun4i-gpadc-iio and the hwmon driver iio_hwmon.
69 called sun4i-gpadc.
88 tablets etc. It has 4 DC/DC step-down regulators, 3 DC/DC step-down
119 over at91-usart-serial driver and usart-spi-driver. Only one function
135 tristate "Atmel HLCDC (High-end LCD Controller)"
172 tristate "X-Powers AC100"
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/linux-5.10/drivers/iio/trigger/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
7 menu "Triggers - standalone"
14 timers as interrupt source.
17 module will be called iio-trig-hrtimer.
26 module will be called iio-trig-interrupt.
29 tristate "STM32 Low-Power Timer Trigger"
32 Select this option to enable STM32 Low-Power Timer Trigger.
33 This can be used as trigger source for STM32 internal ADC
37 module will be called stm32-lptimer-trigger.
40 tristate "STM32 Timer Trigger"
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Dstm32-timer-trigger.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/iio/timer/stm32-timer-trigger.h>
13 #include <linux/mfd/stm32-timers.h>
125 div = (unsigned long long)clk_get_rate(priv->clk); in stm32_timer_start()
135 while (div > priv->max_arr) { in stm32_timer_start()
143 dev_err(priv->dev, "prescaler exceeds the maximum value\n"); in stm32_timer_start()
144 return -EINVAL; in stm32_timer_start()
148 regmap_read(priv->regmap, TIM_CCER, &ccer); in stm32_timer_start()
150 return -EBUSY; in stm32_timer_start()
152 mutex_lock(&priv->lock); in stm32_timer_start()
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/linux-5.10/Documentation/devicetree/bindings/timer/
Dst,stm32-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/st,stm32-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 general-purpose 16 and 32 bits timers bindings
10 - Benjamin Gaignard <benjamin.gaignard@st.com>
14 const: st,stm32-timer
29 - compatible
30 - reg
31 - interrupts
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/linux-5.10/drivers/clocksource/
Dtimer-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Inspired by time-efm32.c from Uwe Kleine-Koenig
23 #include "timer-of.h"
54 * stm32_timer_of_bits_set - set accessor helper
58 * Accessor helper to set the number of bits in the timer-of private
64 struct stm32_timer_private *pd = to->private_data; in stm32_timer_of_bits_set()
66 pd->bits = bits; in stm32_timer_of_bits_set()
70 * stm32_timer_of_bits_get - get accessor helper
73 * Accessor helper to get the number of bits in the timer-of private
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
163 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
186 32-bit free running decrementing counters.
240 bool "Integrator-AP timer driver" if COMPILE_TEST
243 Enables support for the Integrator-AP timer.
251 Support to use the timers of EFM32 SoCs as clock source and clock
276 available on many OMAP-like platforms.
285 It has a 64-bit counter with update rate up to 1000MHz.
286 This counter is accessed via couple of 32-bit memory-mapped registers.
289 bool "Clocksource for STM32 SoCs" if !ARCH_STM32
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/linux-5.10/include/linux/mfd/
Dstm32-lptimer.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * STM32 Low-Power Timer parent driver.
6 * Inspired by Benjamin Gaignard's stm32-timers driver
24 /* STM32_LPTIM_ISR - bit fields */
29 /* STM32_LPTIM_ICR - bit fields */
33 /* STM32_LPTIM_IER - bit flieds */
36 /* STM32_LPTIM_CR - bit fields */
41 /* STM32_LPTIM_CFGR - bit fields */
52 * struct stm32_lptimer - STM32 Low-Power Timer data assigned by parent device
55 * @has_encoder: indicates this Low-Power Timer supports encoder mode
/linux-5.10/Documentation/arm/stm32/
Dstm32f769-overview.rst6 ------------
8 The STM32F769 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @216MHz
12 - 2MB internal flash, 512KBytes internal RAM (+4KB of backup SRAM)
13 - FMC controller to connect SDRAM, NOR and NAND memories
14 - Dual mode QSPI
15 - SD/MMC/SDIO support*2
16 - Ethernet controller
17 - USB OTFG FS & HS controllers
18 - I2C*4, SPI*6, CAN*3 busses support
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Dstm32f746-overview.rst6 ------------
8 The STM32F746 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @216MHz
12 - 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM)
13 - FMC controller to connect SDRAM, NOR and NAND memories
14 - Dual mode QSPI
15 - SD/MMC/SDIO support
16 - Ethernet controller
17 - USB OTFG FS & HS controllers
18 - I2C, SPI, CAN busses support
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/linux-5.10/Documentation/ABI/testing/
Dsysfs-bus-iio-adc-stm325 The STM32 ADC can be configured to use external trigger sources
6 (e.g. timers, pwm or exti gpio). Then, it can be tuned to start
9 - "rising-edge"
10 - "falling-edge"
11 - "both-edges".
/linux-5.10/drivers/counter/
Dstm32-timer-cnt.c1 // SPDX-License-Identifier: GPL-2.0
3 * STM32 Timer Encoder and Counter driver
11 #include <linux/mfd/stm32-timers.h>
40 * enum stm32_count_function - enumerates stm32 timer counter encoder modes
47 STM32_COUNT_SLAVE_MODE_DISABLED = -1,
62 struct stm32_timer_cnt *const priv = counter->priv; in stm32_count_read()
65 regmap_read(priv->regmap, TIM_CNT, &cnt); in stm32_count_read()
75 struct stm32_timer_cnt *const priv = counter->priv; in stm32_count_write()
77 if (val > priv->ceiling) in stm32_count_write()
78 return -EINVAL; in stm32_count_write()
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/linux-5.10/drivers/pwm/
Dpwm-stm32.c1 // SPDX-License-Identifier: GPL-2.0
7 * Inspired by timer-stm32.c from Maxime Coquelin
8 * pwm-atmel.c from Bo Shen
12 #include <linux/mfd/stm32-timers.h>
50 regmap_read(dev->regmap, TIM_CCER, &ccer); in active_channels()
59 return regmap_write(dev->regmap, TIM_CCR1, value); in write_ccrx()
61 return regmap_write(dev->regmap, TIM_CCR2, value); in write_ccrx()
63 return regmap_write(dev->regmap, TIM_CCR3, value); in write_ccrx()
65 return regmap_write(dev->regmap, TIM_CCR4, value); in write_ccrx()
67 return -EINVAL; in write_ccrx()
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/linux-5.10/drivers/watchdog/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 on-line as fast as possible after a lock-up. There's both a watchdog
21 <file:Documentation/watchdog/watchdog-api.rst> in the kernel source.
51 bool "Update boot-enabled watchdog until userspace takes over"
218 tristate "Watchdog device controlled through GPIO-line"
223 controlled through GPIO-line.
341 module will be called mlx-wdt.
375 More details: ARM DEN0029B - Server Base System Architecture (SBSA)
443 The Intel Footbridge chip contains a built-in watchdog circuit. Say Y
451 "If in doubt, leave it out" - say N.
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/linux-5.10/drivers/clk/
Dclk-stm32mp1.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
9 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/stm32mp1-clks.h>
160 "ck_hse", "pll4_r", "clk-hse-div2"
372 /* STM32 Composite clock */
385 struct gate_cfg *gate_cfg = cfg->cfg; in _clk_hw_register_gate()
388 cfg->name, in _clk_hw_register_gate()
389 cfg->parent_name, in _clk_hw_register_gate()
390 cfg->flags, in _clk_hw_register_gate()
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/linux-5.10/
DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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