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/linux-5.10/arch/arm/mach-hisi/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
7 #include <linux/smp.h>
28 writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2)); in hi3xxx_set_cpu_jump()
36 return readl_relaxed(ctrl_base + ((cpu - 1) << 2)); in hi3xxx_get_cpu_jump()
59 u32 offset = 0; in hi3xxx_smp_prepare_cpus() local
73 if (of_property_read_u32(np, "smp-offset", &offset) < 0) { in hi3xxx_smp_prepare_cpus()
74 pr_err("failed to find smp-offset property\n"); in hi3xxx_smp_prepare_cpus()
77 ctrl_base += offset; in hi3xxx_smp_prepare_cpus()
109 writel_relaxed(0xe51ff004, virt); /* ldr pc, [pc, #-4] */ in hix5hd2_set_scu_boot_addr()
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/linux-5.10/Documentation/devicetree/bindings/arm/cpu-enable-method/
Dal,alpine-smp2 Secondary CPU enable-method "al,alpine-smp" binding
5 This document describes the "al,alpine-smp" method for
7 "al,alpine-smp" enable method should be defined in the
10 Enable method name: "al,alpine-smp"
12 Compatible CPUs: "arm,cortex-a15"
17 "al,alpine-cpu-resume" and "al,alpine-nb-service".
26 - compatible : Should contain "al,alpine-cpu-resume".
27 - reg : Offset and length of the register set for the device
30 * Alpine System-Fabric Service Registers
32 The System-Fabric Service Registers allow various operation on CPU and
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/linux-5.10/arch/powerpc/kernel/
Dsmp-tbsync.c1 // SPDX-License-Identifier: GPL-2.0
3 * Smp timebase synchronization for ppc.
11 #include <linux/smp.h>
15 #include <asm/smp.h>
42 tbsync->race_result = add; in enter_contest()
57 tbsync->ack = 1; in smp_generic_take_timebase()
58 while (!tbsync->handshake) in smp_generic_take_timebase()
62 cmd = tbsync->cmd; in smp_generic_take_timebase()
63 tb = tbsync->tb; in smp_generic_take_timebase()
65 tbsync->ack = 0; in smp_generic_take_timebase()
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/linux-5.10/drivers/scsi/isci/
Dscu_task_context.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
68 * enum scu_ssp_task_type - This enumberation defines the various SSP task
77 SCU_TASK_TYPE_SMP_REQUEST, /* /< SMP Request type */
84 * enum scu_sata_task_type - This enumeration defines the various SATA task
222 * MAKE_SCU_CONTEXT_COMMAND_TYPE() -
293 * struct ssp_task_context - This is the SCU hardware definition for an SSP
299 /* OFFSET 0x18 */
303 /* OFFSET 0x1C */
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/linux-5.10/arch/arm/include/asm/
Dprocessor.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1995-1999 Russell King
20 #define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \
41 * Everything usercopied to/from thread_struct is statically-sized, so
44 static inline void arch_thread_struct_whitelist(unsigned long *offset, in arch_thread_struct_whitelist() argument
47 *offset = *size = 0; in arch_thread_struct_whitelist()
57 r7 = regs->ARM_r7; \
58 r8 = regs->ARM_r8; \
59 r9 = regs->ARM_r9; \
61 memset(regs->uregs, 0, sizeof(regs->uregs)); \
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/linux-5.10/sound/synth/emux/
Dsoundfont.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Copyright (c) 1999-2000 Takashi Iwai <tiwai@suse.de>
69 mutex_lock(&sflist->presets_mutex); in lock_preset()
70 spin_lock_irqsave(&sflist->lock, flags); in lock_preset()
71 sflist->presets_locked = 1; in lock_preset()
72 spin_unlock_irqrestore(&sflist->lock, flags); in lock_preset()
83 spin_lock_irqsave(&sflist->lock, flags); in unlock_preset()
84 sflist->presets_locked = 0; in unlock_preset()
85 spin_unlock_irqrestore(&sflist->lock, flags); in unlock_preset()
86 mutex_unlock(&sflist->presets_mutex); in unlock_preset()
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/linux-5.10/Documentation/devicetree/bindings/arm/hisilicon/controller/
Dsysctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wei Xu <xuwei5@hisilicon.com>
19 offset. In addition, the HiP01 system controller has some specific control
23 Hisilicon system controller --> hisilicon,sysctrl
24 HiP01 system controller --> hisilicon,hip01-sysctrl
25 Hi6220 system controller --> hisilicon,hi6220-sysctrl
26 Hi3519 system controller --> hisilicon,hi3519-sysctrl
29 - if:
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/linux-5.10/arch/arm/mach-prima2/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * plat smp support for CSR Marco dual-core SMP SoCs
9 #include <linux/smp.h>
26 /* XXX prima2_pen_release is cargo culted code - DO NOT COPY XXX */
27 volatile int prima2_pen_release = -1;
35 prima2_pen_release = -1; in sirfsoc_secondary_init()
46 { .compatible = "sirf,atlas7-clkc" },
57 return -ENODEV; in sirfsoc_boot_secondary()
61 return -ENOMEM; in sirfsoc_boot_secondary()
65 * at offset 0x2bC, then write the magic number 0x3CAF5D62 to the in sirfsoc_boot_secondary()
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/linux-5.10/drivers/gpio/
Dgpio-xtensa.c1 // SPDX-License-Identifier: GPL-2.0
22 * This driver is currently incompatible with SMP. The GPIO32 extension is not
24 * different set of IO wires. A theoretical SMP aware version of this driver
72 static int xtensa_impwire_get_direction(struct gpio_chip *gc, unsigned offset) in xtensa_impwire_get_direction() argument
77 static int xtensa_impwire_get_value(struct gpio_chip *gc, unsigned offset) in xtensa_impwire_get_value() argument
86 return !!(impwire & BIT(offset)); in xtensa_impwire_get_value()
89 static void xtensa_impwire_set_value(struct gpio_chip *gc, unsigned offset, in xtensa_impwire_set_value() argument
95 static int xtensa_expstate_get_direction(struct gpio_chip *gc, unsigned offset) in xtensa_expstate_get_direction() argument
100 static int xtensa_expstate_get_value(struct gpio_chip *gc, unsigned offset) in xtensa_expstate_get_value() argument
109 return !!(expstate & BIT(offset)); in xtensa_expstate_get_value()
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/linux-5.10/fs/jfs/
Djfs_dtree.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) International Business Machines Corp., 2000-2004
7 * jfs_dtree.c: directory B+-tree manager
9 * B+-tree with variable length key directory:
11 * each directory page is structured as an array of 32-byte
28 * directory starts as a root/leaf page in on-disk inode
41 * case-insensitive directory file system
43 * names are stored in case-sensitive way in leaf entry.
44 * but stored, searched and compared in case-insensitive (uppercase) order
46 * (note that case-sensitive order is BROKEN in storage, e.g.,
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Djfs_xtree.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) International Business Machines Corp., 2000-2005
6 * jfs_xtree.c: extent allocation descriptor B+-tree manager
27 * xtree key/entry comparison: extent offset
30 * -1: k < start of extent
38 ((K) < OFFSET64) ? -1 : 0;\
44 (XAD)->flag = (FLAG);\
58 if ((le16_to_cpu((P)->header.nextindex) < XTENTRYSTART) || \
59 (le16_to_cpu((P)->header.nextindex) > \
60 le16_to_cpu((P)->header.maxentry)) || \
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/linux-5.10/arch/x86/include/asm/
Dalternative.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 * Alternative inline assembly for SMP.
18 * SMP alternatives use the same data structures as the other
20 * UP system running a SMP kernel. The existing apply_alternatives()
21 * works fine for patching a SMP kernel for UP.
23 * The SMP alternative tables can be kept after boot and contain both
24 * UP and SMP versions of the instructions to allow switching back to
25 * SMP at runtime, when hotplugging in a new CPU, which is especially
37 ".long 671f - .\n" /* offset */ \
55 ".long 999b - .\n\t" \
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/linux-5.10/kernel/irq/
Dipi.c1 // SPDX-License-Identifier: GPL-2.0
15 * irq_reserve_ipi() - Setup an IPI to destination cpumask
26 unsigned int nr_irqs, offset; in irq_reserve_ipi() local
32 return -EINVAL; in irq_reserve_ipi()
37 return -EINVAL; in irq_reserve_ipi()
43 return -EINVAL; in irq_reserve_ipi()
54 offset = 0; in irq_reserve_ipi()
64 offset = cpumask_first(dest); in irq_reserve_ipi()
69 next = cpumask_next_zero(offset, dest); in irq_reserve_ipi()
74 return -EINVAL; in irq_reserve_ipi()
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/linux-5.10/arch/arm/mach-ux500/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009 ST-Ericsson.
14 #include <linux/smp.h>
23 #include "db8500-regs.h"
38 np = of_find_compatible_node(NULL, NULL, "ste,dbx500-backupram"); in ux500_smp_prepare_cpus()
50 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); in ux500_smp_prepare_cpus()
73 * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the in ux500_boot_secondary()
74 * backup ram register at offset 0x1FF0, which is what boot rom code in ux500_boot_secondary()
102 CPU_METHOD_OF_DECLARE(ux500_smp, "ste,dbx500-smp", &ux500_smp_ops);
/linux-5.10/arch/sh/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
80 <http://www.linux-sh.org/>.
94 depends on SMP && PREEMPTION
216 prompt "Processor sub-type selection"
222 # SH-2 Processor Support
233 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
235 # SH-2A Processor Support
281 bool "Support MX-G processor"
285 Select MX-G if running on an R8A03022BG part.
287 # SH-3 Processor Support
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/linux-5.10/arch/mips/cavium-octeon/
Dsmp.c6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
10 #include <linux/smp.h>
103 pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu, in octeon_send_ipi_single()
130 if (labi->labi_signature != LABI_SIGNATURE) { in octeon_smp_hotplug_setup()
135 octeon_bootloader_entry_addr = labi->InitTLBStart_addr; in octeon_smp_hotplug_setup()
163 if ((id != coreid) && cvmx_coremask_is_core_set(&sysinfo->core_mask, id)) { in octeon_smp_setup()
194 int plat_post_relocation(long offset) in plat_post_relocation() argument
199 octeon_processor_relocated_kernel_entry = entry + offset; in plat_post_relocation()
213 pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu, in octeon_boot_secondary()
225 count--; in octeon_boot_secondary()
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/linux-5.10/arch/arm/mm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
190 # ARM946E-S
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
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/linux-5.10/arch/x86/kernel/
Dalternative.c1 // SPDX-License-Identifier: GPL-2.0-only
2 #define pr_fmt(fmt) "SMP alternatives: " fmt
21 #include <asm/text-patching.h>
36 #define MAX_PATCH_LEN (255-1)
45 __setup("debug-alternative", debug_alt);
54 __setup("noreplace-smp", setup_noreplace_smp);
71 for (j = 0; j < (len) - 1; j++) \
80 * add to the array the offset that is equal to the sum of all sizes of
212 * the "k8_nops" than with the SDM-recommended NOPs. in arch_init_ideal_nops()
267 len -= noplen; in add_nops()
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/linux-5.10/arch/arm/mach-tegra/
Dsleep.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
12 #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
14 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
16 #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
18 #define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
20 #define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
25 /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
50 /* returns the offset of the flow controller halt register for a cpu */
59 /* returns the offset of the flow controller csr register for a cpu */
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/linux-5.10/drivers/scsi/pm8001/
Dpm8001_hwi.h2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
18 * 3. Neither the names of the above-listed copyright holders nor the names
137 __le32 header; /* Bits [11:0] - Message operation code */
138 /* Bits [15:12] - Message Category */
139 /* Bits [21:16] - Outboundqueue ID for the
141 /* Bits [23:22] - Reserved */
142 /* Bits [28:24] - Buffer Count, indicates how
144 /* Bits [30:29] - Reserved */
145 /* Bits [31] - Message Valid bit */
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/linux-5.10/arch/parisc/include/asm/
Dalternative.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #define ALT_COND_NO_SMP 0x01 /* when running UP instead of SMP */
7 #define ALT_COND_NO_DCACHE 0x02 /* if system has no d-cache */
8 #define ALT_COND_NO_ICACHE 0x04 /* if system has no i-cache */
24 s32 orig_offset; /* offset to original instructions */
35 /* Alternative SMP implementation. */
38 ".word (0b-4-.), 1, " __stringify(cond) "," \
47 .word (from - .), (to - from)/4 ! \
54 .word (from - .), -num_instructions ! \
55 .word cond, (new_instr_ptr - .) ! \
/linux-5.10/arch/x86/include/asm/numachip/
Dnumachip_csr.h6 * Numascale NumaConnect-Specific Header file
17 #include <linux/smp.h>
24 /* 32K CSR space, b15 indicates geo/non-geo */
36 #define NUMACHIP_LCSR_SIZE (NUMACHIP_LCSR_LIM - NUMACHIP_LCSR_BASE + 1)
39 static inline void *lcsr_address(unsigned long offset) in lcsr_address() argument
42 CSR_NODE_BITS(0xfff0) | (offset & CSR_OFFSET_MASK)); in lcsr_address()
45 static inline unsigned int read_lcsr(unsigned long offset) in read_lcsr() argument
47 return swab32(readl(lcsr_address(offset))); in read_lcsr()
50 static inline void write_lcsr(unsigned long offset, unsigned int val) in write_lcsr() argument
52 writel(swab32(val), lcsr_address(offset)); in write_lcsr()
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/linux-5.10/arch/parisc/kernel/
Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 ** SMP Support
6 ** Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
7 ** Copyright (C) 2001,2004 Grant Grundler <grundler@parisc-linux.org>
9 ** Lots of stuff stolen from arch/alpha/kernel/smp.c
10 ** ...and then parisc stole from arch/ia64/kernel/smp.c. Thanks David! :^)
13 ** -grant (1/12/2001)
24 #include <linux/smp.h>
76 /********** SMP inter processor interrupt and communication routines */
127 ops = p->pending_ipi; in ipi_interrupt()
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/linux-5.10/arch/powerpc/platforms/8xx/
Dmicropatch.c1 // SPDX-License-Identifier: GPL-2.0
324 static void __init cpm_write_patch(cpm8xx_t *cp, int offset, uint *patch, int len) in cpm_write_patch() argument
328 memcpy_toio(cp->cp_dpmem + offset, patch, len); in cpm_write_patch()
333 out_be16(&cp->cp_rccr, 0); in cpm_load_patch()
345 iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; in cpm_load_patch()
346 out_be16(&iip->iic_rpbase, rpbase); in cpm_load_patch()
348 /* Put SPI above the IIC, also 32-byte aligned. */ in cpm_load_patch()
349 spp = (struct spi_pram *)&cp->cp_dparam[PROFF_SPI]; in cpm_load_patch()
350 out_be16(&spp->rpbase, (rpbase + sizeof(iic_t) + 31) & ~31); in cpm_load_patch()
353 smc_uart_t *smp; in cpm_load_patch() local
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/linux-5.10/arch/ia64/kernel/
Dcyclone.c1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/smp.h>
34 .mask = (1LL << 40) - 1,
42 u64 offset; /* offset from pageaddr to cyclone_timer register */ in init_cyclone_clock() local
52 offset = (CYCLONE_CBAR_ADDR); in init_cyclone_clock()
53 reg = ioremap(offset, sizeof(u64)); in init_cyclone_clock()
58 return -ENODEV; in init_cyclone_clock()
66 return -ENODEV; in init_cyclone_clock()
70 offset = (base + CYCLONE_PMCC_OFFSET); in init_cyclone_clock()
71 reg = ioremap(offset, sizeof(u64)); in init_cyclone_clock()
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