| /linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | other.json | 6 "EventName": "CPL_CYCLES.RING0",
18 … "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.",
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| /linux/tools/perf/pmu-events/arch/x86/broadwell/ |
| H A D | other.json | 6 "EventName": "CPL_CYCLES.RING0",
18 … "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.",
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| /linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | other.json | 6 "EventName": "CPL_CYCLES.RING0",
18 … "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.",
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| /linux/Documentation/devicetree/bindings/crypto/ |
| H A D | inside-secure,safexcel.yaml | 33 - const: ring0
85 interrupt-names = "ring0", "ring1", "ring2", "ring3", "eip", "mem";
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| /linux/arch/x86/include/asm/xen/ |
| H A D | interface_64.h | 60 * RING0 -> RING3 kernel mode.
64 * However RING0 indicates that the guest kernel should return to itself
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| /linux/tools/perf/pmu-events/arch/x86/haswell/ |
| H A D | other.json | 6 "EventName": "CPL_CYCLES.RING0",
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| /linux/tools/perf/pmu-events/arch/x86/haswellx/ |
| H A D | other.json | 6 "EventName": "CPL_CYCLES.RING0",
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| /linux/tools/perf/pmu-events/arch/x86/ivybridge/ |
| H A D | other.json | 6 "EventName": "CPL_CYCLES.RING0",
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| /linux/tools/perf/pmu-events/arch/x86/ivytown/ |
| H A D | other.json | 6 "EventName": "CPL_CYCLES.RING0",
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| /linux/tools/perf/pmu-events/arch/x86/sandybridge/ |
| H A D | other.json | 6 "EventName": "CPL_CYCLES.RING0",
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| /linux/tools/perf/pmu-events/arch/x86/jaketown/ |
| H A D | other.json | 6 "EventName": "CPL_CYCLES.RING0",
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| /linux/drivers/net/ethernet/amd/ |
| H A D | amd8111e.h | 72 #define XMT_RING_BASE_ADDR0 0x100 /* Transmit ring0 base addr register */
77 #define RCV_RING_BASE_ADDR0 0x120 /* Transmit ring0 base addr register */
84 #define XMT_RING_LEN0 0x140 /* Transmit Ring0 length register */
89 #define RCV_RING_LEN0 0x150 /* Receive Ring0 length register */
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vega10_ih.c | 108 /* enable_intr field is only valid in ring0 */ in vega10_ih_toggle_ring_interrupts()
342 /* Only ring0 supports writeback. On other rings fall back in vega10_ih_get_wptr()
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| H A D | navi10_ih.c | 164 /* enable_intr field is only valid in ring0 */ in navi10_ih_toggle_ring_interrupts()
413 /* Only ring0 supports writeback. On other rings fall back in navi10_ih_get_wptr()
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| H A D | vega20_ih.c | 144 /* enable_intr field is only valid in ring0 */ in vega20_ih_toggle_ring_interrupts()
423 /* Only ring0 supports writeback. On other rings fall back in vega20_ih_get_wptr()
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| H A D | ih_v7_0.c | 138 /* enable_intr field is only valid in ring0 */ in ih_v7_0_toggle_ring_interrupts()
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| H A D | ih_v6_0.c | 166 /* enable_intr field is only valid in ring0 */ in ih_v6_0_toggle_ring_interrupts()
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| H A D | ih_v6_1.c | 138 /* enable_intr field is only valid in ring0 */ in ih_v6_1_toggle_ring_interrupts()
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| H A D | amdgpu_amdkfd_gfx_v10.c | 136 /* TODO - RING0 form of field is obsolete, seems to date back to SI
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| /linux/arch/arm64/boot/dts/marvell/ |
| H A D | armada-37xx.dtsi | 438 interrupt-names = "ring0", "ring1", "ring2",
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| H A D | armada-cp11x.dtsi | 522 interrupt-names = "ring0", "ring1", "ring2", "ring3",
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| /linux/drivers/net/ethernet/socionext/ |
| H A D | sni_ave.c | 52 #define AVE_RXDC0 0x308 /* RX Descriptor Ring0 Configuration */
131 #define AVE_DESCC_RD0 BIT(8) /* Enable Rx descriptor Ring0 */
146 #define AVE_IIRQC_EN0 BIT(27) /* Enable interval interrupt Ring0 */
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| /linux/drivers/scsi/lpfc/ |
| H A D | lpfc_sli.h | 325 uint32_t ring_mask; /* Binds HBQ to a ring e.g. Ring0=b0001,
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt7986a.dtsi | 240 interrupt-names = "ring0", "ring1", "ring2", "ring3";
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| /linux/arch/x86/events/intel/ |
| H A D | lbr.c | 17 #define LBR_KERNEL_BIT 0 /* do not capture at ring0 */
73 #define ARCH_LBR_KERNEL_BIT 1 /* capture at ring0 */
|