| /linux/sound/soc/ux500/ |
| H A D | ux500_msp_i2s.c | 138 writel(temp_reg, msp->registers + MSP_TCF); in set_prot_desc_tx()
166 writel(temp_reg, msp->registers + MSP_RCF); in set_prot_desc_rx()
203 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING; in configure_protocol()
205 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
206 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING; in configure_protocol()
208 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
222 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
223 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
255 writel(temp_reg, msp->registers + MSP_SRG); in setup_bitclk()
261 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
[all …]
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| /linux/Documentation/driver-api/media/drivers/ccs/ |
| H A D | ccs-regs.asc | 18 # general status registers
51 # frame format description registers
91 # analog gain description registers
110 # data format description registers
122 # general set-up registers
170 # integration time registers
174 # analog gain registers
179 # digital gain registers
182 # hdr control registers
203 # clock set-up registers
[all …]
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| /linux/Documentation/trace/coresight/ |
| H A D | coresight-etm4x-reference.rst | 17 ETMv4 registers that they effect. Note the register names are given without
23 :Trace Registers: {CONFIGR + others}
27 other registers to enable the features requested.
40 :Trace Registers: All
50 :Trace Registers: PRGCTLR, All hardware regs.
63 :Trace Registers: None.
75 :Trace Registers: None.
89 :Trace Registers: None.
102 :Trace Registers: ACVR[idx, idx+1], VIIECTLR
125 :Trace Registers: ACVR[idx]
[all …]
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| /linux/drivers/net/can/ctucanfd/ |
| H A D | ctucanfd_kregs.h | 97 /* DEVICE_ID VERSION registers */
102 /* MODE SETTINGS registers */
123 /* STATUS registers */
135 /* COMMAND registers */
144 /* INT_STAT registers */
158 /* INT_ENA_SET registers */
161 /* INT_ENA_CLR registers */
164 /* INT_MASK_SET registers */
167 /* INT_MASK_CLR registers */
170 /* BTR registers */
[all …]
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| /linux/Documentation/devicetree/bindings/crypto/ |
| H A D | hisilicon,hip06-sec.yaml | 20 - description: Registers for backend processing engines
21 - description: Registers for common functionality
22 - description: Registers for queue 0
23 - description: Registers for queue 1
24 - description: Registers for queue 2
25 - description: Registers for queue 3
26 - description: Registers for queue 4
27 - description: Registers for queue 5
28 - description: Registers for queue 6
29 - description: Registers for queue 7
[all …]
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| /linux/drivers/video/fbdev/i810/ |
| H A D | i810_regs.h | 25 * All GC registers are memory-mapped. In addition, the VGA and extended VGA registers
32 /* Instruction and Interrupt Control Registers (01000h 02FFFh) */
60 /* Memory Control Registers (03000h 03FFFh) */
66 /* Span Cursor Registers (04000h 04FFFh) */
69 /* I/O Control Registers (05000h 05FFFh) */
75 /* Clock Control and Power Management Registers (06000h 06FFFh) */
86 /* Overlay Registers (30000h 03FFFFh) */
146 /* LCD/TV-Out and HW DVD Registers (60000h 6FFFFh) */
158 /* Display and Cursor Control Registers (70000h 7FFFFh) */
172 /* VGA Registers */
[all …]
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| /linux/tools/include/uapi/linux/ |
| H A D | elf.h | 398 #define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */
399 #define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */
400 #define NT_PPC_VSX 0x102 /* PowerPC VSX registers */
404 #define NT_PPC_EBB 0x106 /* Event Based Branch Registers */
405 #define NT_PPC_PMU 0x107 /* Performance Monitor Registers */
406 #define NT_PPC_TM_CGPR 0x108 /* TM checkpointed GPR Registers */
407 #define NT_PPC_TM_CFPR 0x109 /* TM checkpointed FPR Registers */
408 #define NT_PPC_TM_CVMX 0x10a /* TM checkpointed VMX Registers */
409 #define NT_PPC_TM_CVSX 0x10b /* TM checkpointed VSX Registers */
410 #define NT_PPC_TM_SPR 0x10c /* TM Special Purpose Registers */
[all …]
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| /linux/tools/testing/selftests/vfio/lib/drivers/ioat/ |
| H A D | ioat.c | 13 #include "registers.h"
67 void *registers = ioat_channel_registers(device); in ioat_clear_errors() local
76 errors = readl(registers + IOAT_CHANERR_OFFSET); in ioat_clear_errors()
77 writel(errors, registers + IOAT_CHANERR_OFFSET); in ioat_clear_errors()
82 void *registers = ioat_channel_registers(device); in ioat_reset() local
88 writeb(IOAT_CHANCMD_RESET, registers + IOAT2_CHANCMD_OFFSET); in ioat_reset()
91 chancmd = readb(registers + IOAT2_CHANCMD_OFFSET); in ioat_reset()
99 VFIO_ASSERT_EQ(ioat_channel_status(registers), IOAT_CHANSTS_HALTED); in ioat_reset()
136 void *registers = ioat_channel_registers(device); in ioat_handle_error() local
142 readl(registers + IOAT_CHANERR_OFFSET), in ioat_handle_error()
[all …]
|
| /linux/include/uapi/linux/ |
| H A D | elf.h | 420 #define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */
422 #define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */
424 #define NT_PPC_VSX 0x102 /* PowerPC VSX registers */
432 #define NT_PPC_EBB 0x106 /* Event Based Branch Registers */
434 #define NT_PPC_PMU 0x107 /* Performance Monitor Registers */
436 #define NT_PPC_TM_CGPR 0x108 /* TM checkpointed GPR Registers */
438 #define NT_PPC_TM_CFPR 0x109 /* TM checkpointed FPR Registers */
440 #define NT_PPC_TM_CVMX 0x10a /* TM checkpointed VMX Registers */
442 #define NT_PPC_TM_CVSX 0x10b /* TM checkpointed VSX Registers */
444 #define NT_PPC_TM_SPR 0x10c /* TM Special Purpose Registers */
[all …]
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| /linux/drivers/scsi/smartpqi/ |
| H A D | smartpqi_sis.c | 110 status = readl(&ctrl_info->registers->sis_firmware_status); in sis_wait_for_ctrl_ready_with_timeout()
116 &ctrl_info->registers->sis_mailbox[7])); in sis_wait_for_ctrl_ready_with_timeout()
151 status = readl(&ctrl_info->registers->sis_firmware_status); in sis_is_firmware_running()
161 readl(&ctrl_info->registers->sis_mailbox[7])); in sis_is_firmware_running()
168 return readl(&ctrl_info->registers->sis_firmware_status) & in sis_is_kernel_up()
174 return readl(&ctrl_info->registers->sis_product_identifier); in sis_get_product_id()
185 struct pqi_ctrl_registers __iomem *registers; in sis_send_sync_cmd() local
191 registers = ctrl_info->registers; in sis_send_sync_cmd()
194 writel(cmd, ®isters->sis_mailbox[0]); in sis_send_sync_cmd()
201 writel(params->mailbox[i], ®isters->sis_mailbox[i]); in sis_send_sync_cmd()
[all …]
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| /linux/drivers/accel/habanalabs/include/gaudi2/arc/ |
| H A D | gaudi2_arc_common_packets.h | 99 * Extension registers
104 * Extension registers
111 * Extension registers
118 * Extension registers
125 * Extension registers
133 * Extension registers
141 * Extension registers
149 * Extension registers
157 * Extension registers
163 * Extension registers
[all …]
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| /linux/Documentation/devicetree/bindings/display/msm/ |
| H A D | gmu.yaml | 100 - description: Core GMU registers
101 - description: GMU PDC registers
102 - description: GMU PDC sequence registers
131 - description: Core GMU registers
132 - description: Resource controller registers
133 - description: GMU PDC registers
168 - description: Core GMU registers
169 - description: Resource controller registers
170 - description: GMU PDC registers
205 - description: Core GMU registers
[all …]
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| /linux/drivers/crypto/intel/qat/qat_common/ |
| H A D | adf_gen6_tl.h | 88 * @ath_slices: array of Authentication slices utilization registers
89 * @cnv_slices: array of Compression slices utilization registers
90 * @dcprz_slices: array of Decompression slices utilization registers
91 * @pke_slices: array of PKE slices utilization registers
92 * @ucs_slices: array of UCS slices utilization registers
93 * @wat_slices: array of Wireless Authentication slices utilization registers
94 * @wcp_slices: array of Wireless Cipher slices utilization registers
95 * @ath_cmdq: array of Authentication cmdq telemetry registers
96 * @cnv_cmdq: array of Compression cmdq telemetry registers
97 * @dcprz_cmdq: array of Decomopression cmdq telemetry registers
[all …]
|
| /linux/sound/soc/codecs/ |
| H A D | tlv320aic3x.h | 57 /* ADC PGA Gain control registers */
60 /* MIC3 control registers */
63 /* Line1 Input control registers */
68 /* Line2 Input control registers */
74 /* AGC Control Registers A, B, C */
82 /* DAC Power and Left High Power Output control registers */
85 /* Right High Power Output control registers */
89 /* DAC Output Switching control registers */
91 /* High Power Output Driver Pop Reduction registers */
93 /* DAC Digital control registers */
[all …]
|
| /linux/drivers/net/ethernet/intel/ice/ |
| H A D | ice_ptp_hw.h | 112 * P_REG_DESK_PAR* registers may represent different clock markers at
134 * struct ice_eth56g_mac_reg_cfg - MAC config values for specific PTP registers
147 * All fixed point registers except Rx offset are 23 bit unsigned ints with
329 * change, such as an update to the CGU registers.
444 /* Timestamp memory reset registers */
449 /* Timestamp availability status registers */
453 /* Tx FIFO status registers */
461 /* Interrupt control Config registers */
469 /* Tx Timestamp data registers */
476 /* Timestamp init registers */
[all …]
|
| /linux/Documentation/devicetree/bindings/dma/ti/ |
| H A D | k3-bcdma.yaml | 21 directly to memory mapped registers or area.
28 PDMAs can be configured via BCDMA split channel's peer registers to match with
146 - description: BCDMA Control /Status Registers region
147 - description: RX Channel Realtime Registers region
148 - description: Ring Realtime Registers region
169 - description: BCDMA Control /Status Registers region
170 - description: Block Copy Channel Realtime Registers region
171 - description: RX Channel Realtime Registers region
172 - description: TX Channel Realtime Registers region
173 - description: Ring Realtime Registers region
[all …]
|
| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | nxp,s32g2-siul2-pinctrl.yaml | 21 IMCR registers need to be revealed for kernel to configure pinmux.
41 - description: MSCR registers group 0 in SIUL2_0
42 - description: MSCR registers group 1 in SIUL2_1
43 - description: MSCR registers group 2 in SIUL2_1
44 - description: IMCR registers group 0 in SIUL2_0
45 - description: IMCR registers group 1 in SIUL2_1
46 - description: IMCR registers group 2 in SIUL2_1
96 /* MSCR0-MSCR101 registers on siul2_0 */
98 /* MSCR112-MSCR122 registers on siul2_1 */
100 /* MSCR144-MSCR190 registers on siul2_1 */
[all …]
|
| /linux/arch/xtensa/variants/csp/include/variant/ |
| H A D | tie-asm.h | 58 * (not including zero-overhead loop registers).
62 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
63 * registers are clobbered, the remaining are unused).
70 * select Select what category(ies) of registers to store, as a bitmask
71 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
72 * alloc Select what category(ies) of registers to allocate; if any
74 * the corresponding registers is skipped without doing any store.
78 // Optional global registers used by default by the compiler:
88 // Optional caller-saved registers used by default by the compiler:
100 // Optional caller-saved registers not used by default by the compiler:
[all …]
|
| /linux/arch/xtensa/variants/de212/include/variant/ |
| H A D | tie-asm.h | 58 * (not including zero-overhead loop registers).
62 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
63 * registers are clobbered, the remaining are unused).
70 * select Select what category(ies) of registers to store, as a bitmask
71 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
72 * alloc Select what category(ies) of registers to allocate; if any
74 * the corresponding registers is skipped without doing any store.
78 // Optional caller-saved registers used by default by the compiler:
90 // Optional caller-saved registers not used by default by the compiler:
112 * (not including zero-overhead loop registers).
[all …]
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| /linux/drivers/media/radio/si470x/ |
| H A D | radio-si470x-common.c | 185 radio->registers[SYSCONFIG2] &= ~SYSCONFIG2_BAND; in si470x_set_band()
186 radio->registers[SYSCONFIG2] |= radio->band << 6; in si470x_set_band()
203 if ((radio->registers[POWERCFG] & (POWERCFG_ENABLE|POWERCFG_DMUTE)) in si470x_set_chan()
209 radio->registers[CHANNEL] &= ~CHANNEL_CHAN; in si470x_set_chan()
210 radio->registers[CHANNEL] |= CHANNEL_TUNE | chan; in si470x_set_chan()
222 if ((radio->registers[STATUSRSSI] & STATUSRSSI_STC) == 0) in si470x_set_chan()
229 radio->registers[CHANNEL] &= ~CHANNEL_TUNE; in si470x_set_chan()
242 switch ((radio->registers[SYSCONFIG2] & SYSCONFIG2_SPACE) >> 4) { in si470x_get_step()
265 chan = radio->registers[READCHAN] & READCHAN_READCHAN; in si470x_get_freq()
327 radio->registers[POWERCFG] |= POWERCFG_SEEK; in si470x_set_seek()
[all …]
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| /linux/arch/mips/include/uapi/asm/ |
| H A D | kvm.h | 49 * registers. The id field is broken down as follows:
55 * Register set = 0: GP registers from kvm_regs (see definitions below).
57 * Register set = 1: CP0 registers.
60 * COP0 register set = 0: Main CP0 registers.
67 * Register set = 2: KVM specific registers (see definitions below).
69 * Register set = 3: FPU / MSA registers (see definitions below).
71 * Other sets registers may be added in the future. Each set would
82 * KVM_REG_MIPS_GP - General purpose registers from kvm_regs.
124 * KVM_REG_MIPS_CP0 - Coprocessor 0 registers.
133 * KVM_REG_MIPS_KVM - KVM specific control registers.
[all …]
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| /linux/arch/xtensa/variants/test_kc705_be/include/variant/ |
| H A D | tie-asm.h | 58 * (not including zero-overhead loop registers).
62 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
63 * registers are clobbered, the remaining are unused).
70 * select Select what category(ies) of registers to store, as a bitmask
71 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
72 * alloc Select what category(ies) of registers to allocate; if any
74 * the corresponding registers is skipped without doing any store.
78 // Optional global registers used by default by the compiler:
88 // Optional caller-saved registers used by default by the compiler:
100 // Optional caller-saved registers not used by default by the compiler:
[all …]
|
| /linux/arch/riscv/include/uapi/asm/ |
| H A D | kvm.h | 44 /* definition of registers in kvm_run */
52 /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
64 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
74 /* General CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
89 /* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
105 /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
223 /* SBI STA extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
235 /* SBI FWFT extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
251 /* Config registers are mapped as type 1 */
256 /* Core registers are mapped as type 2 */
[all …]
|
| /linux/arch/xtensa/variants/dc233c/include/variant/ |
| H A D | tie-asm.h | 59 * (not including zero-overhead loop registers).
63 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
64 * registers are clobbered, the remaining are unused).
71 * select Select what category(ies) of registers to store, as a bitmask
72 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
73 * alloc Select what category(ies) of registers to allocate; if any
75 * the corresponding registers is skipped without doing any store.
89 // Optional caller-saved registers used by default by the compiler:
101 // Optional caller-saved registers not used by default by the compiler:
123 * (not including zero-overhead loop registers).
[all …]
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| /linux/Documentation/devicetree/bindings/powerpc/nintendo/ |
| H A D | wii.txt | 31 - reg : should contain the VI registers location and length
42 - reg : should contain the PI registers location and length
64 - reg : should contain the DSP registers location and length
76 - reg : should contain the SI registers location and length
87 - reg : should contain the AI registers location and length
97 - reg : should contain the EXI registers location and length
107 - reg : should contain the EHCI registers location and length
117 - reg : should contain the SDHCI registers location and length
126 - reg : should contain the IPC registers location and length
138 - reg : should contain the controller registers location and length
[all …]
|