| /linux-5.10/include/linux/phy/ |
| D | phy.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * phy.h -- generic phy header file
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
15 #include <linux/device.h>
19 #include <linux/phy/phy-dp.h>
20 #include <linux/phy/phy-mipi-dphy.h>
22 struct phy;
48 * union phy_configure_opts - Opaque generic phy configuration
51 * the MIPI_DPHY phy mode.
61 * struct phy_ops - set of function pointers for performing phy operations
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| /linux-5.10/drivers/phy/ |
| D | phy-core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-core.c -- Generic Phy framework.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
14 #include <linux/device.h>
17 #include <linux/phy/phy.h>
28 static void devm_phy_release(struct device *dev, void *res) in devm_phy_release()
30 struct phy *phy = *(struct phy **)res; in devm_phy_release() local
32 phy_put(dev, phy); in devm_phy_release()
35 static void devm_phy_provider_release(struct device *dev, void *res) in devm_phy_provider_release()
42 static void devm_phy_consume(struct device *dev, void *res) in devm_phy_consume()
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| /linux-5.10/Documentation/driver-api/phy/ |
| D | phy.rst | 2 PHY subsystem
7 This document explains the Generic PHY Framework along with the APIs provided,
8 and how-to-use.
13 *PHY* is the abbreviation for physical layer. It is used to connect a device
14 to the physical medium e.g., the USB controller has a PHY to provide functions
15 such as serialization, de-serialization, encoding, decoding and is responsible
17 controllers have PHY functionality embedded into it and others use an external
18 PHY. Other peripherals that use PHY include Wireless LAN, Ethernet,
21 The intention of creating this framework is to bring the PHY drivers spread
22 all over the Linux kernel to drivers/phy to increase code re-use and for
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| /linux-5.10/drivers/net/mdio/ |
| D | of_mdio.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * OF helpers for the MDIO (Ethernet PHY) API
7 * This file provides helper functions for extracting PHY device information
8 * out of the OpenFirmware device tree and using it to populate an mii_bus.
12 #include <linux/device.h>
15 #include <linux/phy.h>
28 /* Extract the clause 22 phy ID from the compatible string of the form
29 * ethernet-phy-idAAAA.BBBB */
30 static int of_get_phy_id(struct device_node *device, u32 *phy_id) in of_get_phy_id() argument
36 of_property_for_each_string(device, "compatible", prop, cp) { in of_get_phy_id()
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| /linux-5.10/drivers/usb/phy/ |
| D | phy.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * phy.c -- USB phy handling
5 * Copyright (C) 2004-2013 Texas Instruments
10 #include <linux/device.h>
15 #include <linux/usb/phy.h>
33 struct usb_phy *phy; member
48 struct usb_phy *phy = NULL; in __usb_find_phy() local
50 list_for_each_entry(phy, list, head) { in __usb_find_phy()
51 if (phy->type != type) in __usb_find_phy()
54 return phy; in __usb_find_phy()
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| D | phy-tahvo.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2005-2006 Nokia Corporation
18 #include <linux/extcon-provider.h>
26 #define DRIVER_NAME "tahvo-usb"
46 struct usb_phy phy; member
62 static ssize_t vbus_show(struct device *device, in vbus_show() argument
65 struct tahvo_usb *tu = dev_get_drvdata(device); in vbus_show()
66 return sprintf(buf, "%s\n", tu->vbus_state ? "on" : "off"); in vbus_show()
72 struct retu_dev *rdev = dev_get_drvdata(tu->pt_dev->dev.parent); in check_vbus_state()
77 switch (tu->phy.otg->state) { in check_vbus_state()
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| /linux-5.10/drivers/scsi/ |
| D | scsi_transport_sas.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2005-2006 Dell Inc.
13 * introduces two additional intermediate objects: The SAS PHY
14 * as represented by struct sas_phy defines an "outgoing" PHY on
15 * a SAS HBA or Expander, and the SAS remote PHY represented by
16 * struct sas_rphy defines an "incoming" PHY on a SAS Expander or
17 * end device. Note that this is purely a software concept, the
18 * underlying hardware for a PHY and a remote PHY is the exactly
52 #define to_sas_host_attrs(host) ((struct sas_host_attrs *)(host)->shost_data)
101 return -EINVAL; \
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| /linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | phy-hisi-inno-usb2.txt | 1 Device tree bindings for HiSilicon INNO USB2 PHY
4 - compatible: Should be one of the following strings:
5 "hisilicon,inno-usb2-phy",
6 "hisilicon,hi3798cv200-usb2-phy".
7 - reg: Should be the address space for PHY configuration register in peripheral
9 - clocks: The phandle and clock specifier pair for INNO USB2 PHY device
11 - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
13 - #address-cells: Must be 1.
14 - #size-cells: Must be 0.
16 The INNO USB2 PHY device should be a child node of peripheral controller that
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| D | rcar-gen2-phy.txt | 1 * Renesas R-Car generation 2 USB PHY
3 This file provides information on what the device node for the R-Car generation
4 2 USB PHY contains.
7 - compatible: "renesas,usb-phy-r8a7742" if the device is a part of R8A7742 SoC.
8 "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC.
9 "renesas,usb-phy-r8a7744" if the device is a part of R8A7744 SoC.
10 "renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC.
11 "renesas,usb-phy-r8a77470" if the device is a part of R8A77470 SoC.
12 "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
13 "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
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| D | phy-bindings.txt | 1 This document explains only the device tree data binding. For general
2 information about PHY subsystem refer to Documentation/driver-api/phy/phy.rst
4 PHY device node
8 #phy-cells: Number of cells in a PHY specifier; The meaning of all those
9 cells is defined by the binding for the phy node. The PHY
11 PHY.
14 phy-supply: Phandle to a regulator that provides power to the PHY. This
15 regulator will be managed during the PHY power on/off sequence.
19 phys: phy {
24 #phy-cells = <1>;
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| D | samsung-phy.txt | 2 -------------------------------------------------
5 - compatible : should be one of the listed compatibles:
6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
12 - syscon - phandle to the PMU system controller
14 In case of exynos5433 compatible PHY:
15 - samsung,pmu-syscon - phandle to the PMU system controller
16 - samsung,disp-sysreg - phandle to the DISP system registers controller
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| D | phy-da8xx-usb.txt | 1 TI DA8xx/OMAP-L1xx/AM18xx USB PHY
4 - compatible: must be "ti,da830-usb-phy".
5 - #phy-cells: must be 1.
7 This device controls the PHY for both the USB 1.1 OHCI and USB 2.0 OTG
8 controllers on DA8xx SoCs. Consumers of this device should use index 0 for
9 the USB 2.0 phy device and index 1 for the USB 1.1 phy device.
11 It also requires a "syscon" node with compatible = "ti,da830-cfgchip", "syscon"
17 compatible = "ti,da830-cfgchip", "syscon";
21 usb_phy: usb-phy {
22 compatible = "ti,da830-usb-phy";
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| /linux-5.10/drivers/staging/greybus/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
8 Select this option if you have a device that follows the
12 will be called gb-audio.ko
18 Select this option if you have a Toshiba APB device that has I2S
19 ports and acts as a Greybus "Dummy codec". This device is a
20 bridge from an APB-I2S port to a Unipro network.
23 will be called gb-audio-codec.ko
29 Select this option if you have a device that follows the
33 will be called gb-bootrom.ko
39 Select this option if you have a device that follows the
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| /linux-5.10/Documentation/networking/ |
| D | phy.rst | 2 PHY Abstraction Layer
10 PHY. The PHY concerns itself with negotiating link parameters with the link
17 the PHY management code with the network driver. This has resulted in large
23 accessed are, in fact, busses, the PHY Abstraction Layer treats them as such.
26 #. Increase code-reuse
27 #. Increase overall code-maintainability
30 Basically, this layer is meant to provide an interface to PHY devices which
37 Most network devices are connected to a PHY by means of a management bus.
40 registered as a distinct device.
47 mii_id is the address on the bus for the PHY, and regnum is the register
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| /linux-5.10/drivers/scsi/smartpqi/ |
| D | smartpqi_sas_transport.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * driver for Microsemi PQI-based storage controllers
4 * Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries
5 * Copyright (c) 2016-2018 Microsemi Corporation
6 * Copyright (c) 2016 PMC-Sierra, Inc.
13 #include <linux/bsg-lib.h>
23 struct sas_phy *phy; in pqi_alloc_sas_phy() local
29 phy = sas_phy_alloc(pqi_sas_port->parent_node->parent_dev, in pqi_alloc_sas_phy()
30 pqi_sas_port->next_phy_index); in pqi_alloc_sas_phy()
31 if (!phy) { in pqi_alloc_sas_phy()
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| /linux-5.10/Documentation/devicetree/bindings/display/msm/ |
| D | dsi.txt | 5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
25 - assigned-clocks: Parents of "byte" and "pixel" for the given platform.
26 - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
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| /linux-5.10/Documentation/devicetree/bindings/net/ |
| D | fsl-enetc.txt | 1 * ENETC ethernet device tree bindings
5 below device tree bindings.
9 - reg : Specifies PCIe Device Number and Function
10 Number of the ENETC endpoint device, according
12 - compatible : Should be "fsl,enetc".
14 1. The ENETC external port is connected to a MDIO configurable phy
18 In this case, the ENETC node should include a "mdio" sub-node
19 that in turn should contain the "ethernet-phy" node describing the
20 external phy. Below properties are required, their bindings
22 Documentation/devicetree/bindings/net/phy.txt.
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| D | cpsw.txt | 1 TI SoC Ethernet Switch Controller Device Tree Bindings
2 ------------------------------------------------------
5 - compatible : Should be one of the below:-
7 "ti,am335x-cpsw" for AM335x controllers
8 "ti,am4372-cpsw" for AM437x controllers
9 "ti,dra7-cpsw" for DRA7x controllers
10 - reg : physical base address and size of the cpsw
12 - interrupts : property with a value describing the interrupt
14 - cpdma_channels : Specifies number of channels in CPDMA
15 - ale_entries : Specifies No of entries ALE can hold
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| D | ibm,emac.txt | 8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
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| /linux-5.10/drivers/phy/broadcom/ |
| D | phy-bcm-cygnus-pcie.c | 18 #include <linux/phy/phy.h>
34 * struct cygnus_pcie_phy - Cygnus PCIe PHY device
35 * @core: pointer to the Cygnus PCIe PHY core control
36 * @id: internal ID to identify the Cygnus PCIe PHY
37 * @phy: pointer to the kernel PHY device
42 struct phy *phy; member
46 * struct cygnus_pcie_phy_core - Cygnus PCIe PHY core control
47 * @dev: pointer to device
50 * @phys: pointer to Cygnus PHY device
53 struct device *dev;
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| D | phy-bcm-sr-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
12 #include <linux/phy/phy.h>
18 #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
40 * struct sr_pcie_phy - Stingray PCIe PHY
42 * @core: pointer to the Stingray PCIe PHY core control
43 * @index: PHY index
44 * @phy: pointer to the kernel PHY device
49 struct phy *phy; member
53 * struct sr_pcie_phy_core - Stingray PCIe PHY core control
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| /linux-5.10/drivers/usb/core/ |
| D | phy.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * multiple (actual) PHY devices. This is comes handy when initializing
10 #include <linux/device.h>
12 #include <linux/phy/phy.h>
15 #include "phy.h"
18 struct phy *phy; member
22 static int usb_phy_roothub_add_phy(struct device *dev, int index, in usb_phy_roothub_add_phy()
26 struct phy *phy; in usb_phy_roothub_add_phy() local
28 phy = devm_of_phy_get_by_index(dev, dev->of_node, index); in usb_phy_roothub_add_phy()
29 if (IS_ERR(phy)) { in usb_phy_roothub_add_phy()
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| /linux-5.10/drivers/dma/ |
| D | mmp_pdma.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
15 #include <linux/device.h>
21 #include <linux/dma/mmp-pdma.h>
34 #define DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */
36 #define DCSR_REQPEND BIT(8) /* Request Pending (read-only) */
37 #define DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */
63 #define DCMD_ENDIAN BIT(18) /* Device Endian-ness. */
70 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
91 struct device *dev;
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| /linux-5.10/drivers/phy/ralink/ |
| D | phy-ralink-usb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <linux/phy/phy.h>
56 struct phy *phy; member
61 static void u2_phy_w32(struct ralink_usb_phy *phy, u32 val, u32 reg) in u2_phy_w32() argument
63 writel(val, phy->base + reg); in u2_phy_w32()
66 static u32 u2_phy_r32(struct ralink_usb_phy *phy, u32 reg) in u2_phy_r32() argument
68 return readl(phy->base + reg); in u2_phy_r32()
71 static void ralink_usb_phy_init(struct ralink_usb_phy *phy) in ralink_usb_phy_init() argument
73 u2_phy_r32(phy, OFS_U2_PHY_AC2); in ralink_usb_phy_init()
74 u2_phy_r32(phy, OFS_U2_PHY_ACR0); in ralink_usb_phy_init()
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| /linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | msm-hsusb.txt | 6 - compatible: Should contain "qcom,ehci-host"
7 - regs: offset and length of the register set in the memory map
8 - usb-phy: phandle for the PHY device
10 Example EHCI controller device node:
13 compatible = "qcom,ehci-host";
15 usb-phy = <&usb_otg>;
18 USB PHY with optional OTG:
21 - compatible: Should contain:
22 "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
23 "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
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