/linux/drivers/gpu/drm/msm/registers/adreno/ |
H A D | a7xx_perfcntrs.xml | 9 <enum name="a7xx_cp_perfcounter_select"> 10 <value value="0" name="A7XX_PERF_CP_ALWAYS_COUNT"/> 11 <value value="1" name="A7XX_PERF_CP_BUSY_GFX_CORE_IDLE"/> 12 <value value="2" name="A7XX_PERF_CP_BUSY_CYCLES"/> 13 <value value="3" name="A7XX_PERF_CP_NUM_PREEMPTIONS"/> 14 <value value="4" name="A7XX_PERF_CP_PREEMPTION_REACTION_DELAY"/> 15 <value value="5" name="A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/> 16 <value value="6" name="A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME"/> 17 <value value="7" name="A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/> 18 <value value="8" name [all...] |
H A D | a2xx.xml | 10 <enum name="a2xx_rb_dither_type"> 11 <value name="DITHER_PIXEL" value="0"/> 12 <value name="DITHER_SUBPIXEL" value="1"/> 15 <enum name="a2xx_colorformatx"> 16 <value name="COLORX_4_4_4_4" value="0"/> 17 <value name="COLORX_1_5_5_5" value="1"/> 18 <value name="COLORX_5_6_5" value="2"/> 19 <value name="COLORX_8" value="3"/> 20 <value name="COLORX_8_8" value="4"/> 21 <value name [all...] |
H A D | a6xx_perfcntrs.xml | 9 <enum name="a6xx_cp_perfcounter_select"> 10 <value value="0" name="PERF_CP_ALWAYS_COUNT"/> 11 <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/> 12 <value value="2" name="PERF_CP_BUSY_CYCLES"/> 13 <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/> 14 <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/> 15 <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/> 16 <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/> 17 <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/> 18 <value value="8" name [all...] |
H A D | a5xx.xml | 9 <enum name="a5xx_color_fmt"> 10 <value value="0x02" name="RB5_A8_UNORM"/> 11 <value value="0x03" name="RB5_R8_UNORM"/> 12 <value value="0x04" name="RB5_R8_SNORM"/> 13 <value value="0x05" name="RB5_R8_UINT"/> 14 <value value="0x06" name="RB5_R8_SINT"/> 15 <value value="0x08" name="RB5_R4G4B4A4_UNORM"/> 16 <value value="0x0a" name="RB5_R5G5B5A1_UNORM"/> 17 <value value="0x0e" name="RB5_R5G6B5_UNORM"/> 18 <value value="0x0f" name [all...] |
H A D | a4xx.xml | 9 <enum name="a4xx_color_fmt"> 10 <value name="RB4_A8_UNORM" value="0x01"/> 11 <value name="RB4_R8_UNORM" value="0x02"/> 12 <value name="RB4_R8_SNORM" value="0x03"/> 13 <value name="RB4_R8_UINT" value="0x04"/> 14 <value name="RB4_R8_SINT" value="0x05"/> 16 <value name="RB4_R4G4B4A4_UNORM" value="0x08"/> 17 <value name="RB4_R5G5B5A1_UNORM" value="0x0a"/> 18 <value name="RB4_R5G6B5_UNORM" value="0x0e"/> 19 <value name [all...] |
H A D | a7xx_enums.xml | 9 <enum name="a7xx_statetype_id"> 10 <value value="0" name="A7XX_TP0_NCTX_REG"/> 11 <value value="1" name="A7XX_TP0_CTX0_3D_CVS_REG"/> 12 <value value="2" name="A7XX_TP0_CTX0_3D_CPS_REG"/> 13 <value value="3" name="A7XX_TP0_CTX1_3D_CVS_REG"/> 14 <value value="4" name="A7XX_TP0_CTX1_3D_CPS_REG"/> 15 <value value="5" name="A7XX_TP0_CTX2_3D_CPS_REG"/> 16 <value value="6" name="A7XX_TP0_CTX3_3D_CPS_REG"/> 17 <value value="9" name="A7XX_TP0_TMO_DATA"/> 18 <value value="10" name [all...] |
H A D | a3xx.xml | 9 <enum name="a3xx_tile_mode"> 10 <value name="LINEAR" value="0"/> 11 <value name="TILE_4X4" value="1"/> <!-- "normal" case for textures --> 12 <value name="TILE_32X32" value="2"/> <!-- only used in GMEM --> 13 <value name="TILE_4X2" value="3"/> <!-- only used for CrCb --> 16 <enum name="a3xx_state_block_id"> 17 <value name="HLSQ_BLOCK_ID_TP_TEX" value="2"/> 18 <value name="HLSQ_BLOCK_ID_TP_MIPMAP" value="3"/> 19 <value name="HLSQ_BLOCK_ID_SP_VS" value="4"/> 20 <value name [all...] |
H A D | adreno_common.xml | 7 <enum name="chip" bare="yes"> 8 <value name="A2XX" value="2"/> 9 <value name="A3XX" value="3"/> 10 <value name="A4XX" value="4"/> 11 <value name="A5XX" value="5"/> 12 <value name="A6XX" value="6"/> 13 <value name="A7XX" value="7"/> 16 <enum name="adreno_pa_su_sc_draw"> 17 <value name="PC_DRAW_POINTS" value="0"/> 18 <value name [all...] |
H A D | a6xx_gmu.xml | 8 <domain name="A6XX" width="32" prefix="variant" varset="chip"> 10 <bitset name="A6XX_GMU_GPU_IDLE_STATUS"> 11 <bitfield name="BUSY_IGN_AHB" pos="23"/> 12 <bitfield name="CX_GX_CPU_BUSY_IGN_AHB" pos="30"/> 15 <bitset name="A6XX_GMU_OOB"> 16 <bitfield name="BOOT_SLUMBER_SET_MASK" pos="22"/> 17 <bitfield name="BOOT_SLUMBER_CHECK_MASK" pos="30"/> 18 <bitfield name="BOOT_SLUMBER_CLEAR_MASK" pos="30"/> 19 <bitfield name="DCVS_SET_MASK" pos="23"/> 20 <bitfield name [all...] |
H A D | a6xx_enums.xml | 9 <enum name="a6xx_tile_mode"> 10 <value name="TILE6_LINEAR" value="0"/> 11 <value name="TILE6_2" value="2"/> 12 <value name="TILE6_3" value="3"/> 15 <enum name="a6xx_format"> 16 <value value="0x02" name="FMT6_A8_UNORM"/> 17 <value value="0x03" name="FMT6_8_UNORM"/> 18 <value value="0x04" name="FMT6_8_SNORM"/> 19 <value value="0x05" name="FMT6_8_UINT"/> 20 <value value="0x06" name [all...] |
H A D | a6xx.xml | 28 <domain name="A6XX" width="32" prefix="variant" varset="chip"> 29 <bitset name="A6XX_RBBM_INT_0_MASK" inline="no" varset="chip"> 30 <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/> 31 <bitfield name="CP_AHB_ERROR" pos="1" type="boolean"/> 32 <bitfield name="CP_IPC_INTR_0" pos="4" type="boolean" variants="A7XX-"/> 33 <bitfield name="CP_IPC_INTR_1" pos="5" type="boolean" variants="A7XX-"/> 34 <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6" type="boolean"/> 35 <bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/> 36 <bitfield name="CP_SW" pos="8" type="boolean"/> 37 <bitfield name [all...] |
H A D | adreno_pm4.xml | 8 <enum name="vgt_event_type" varset="chip"> 9 <value name="VS_DEALLOC" value="0"/> 10 <value name="PS_DEALLOC" value="1" variants="A2XX-A6XX"/> 11 <value name="VS_DONE_TS" value="2"/> 12 <value name="PS_DONE_TS" value="3"/> 17 <value name="CACHE_FLUSH_TS" value="4"/> 18 <value name="CONTEXT_DONE" value="5"/> 19 <value name="CACHE_FLUSH" value="6" variants="A2XX-A4XX"/> 20 <value name="VIZQUERY_START" value="7" variants="A2XX"/> 21 <value name [all...] |
/linux/Documentation/netlink/specs/ |
H A D | rt-link.yaml | 3 name: rt-link 13 name: ifinfo-flags 16 enum-name: net-device-flags 17 name-prefix: iff- 20 name: up 22 name: broadcast 24 name: debug 26 name: loopback 28 name: point-to-point 30 name [all...] |
H A D | tc.yaml | 3 name: tc 14 name: tcmsg 19 name: family 22 name: pad 26 name: ifindex 29 name: handle 32 name: parent 35 name: info 38 name: cls-flags 39 enum-name [all...] |
H A D | nl80211.yaml | 3 name: nl80211 11 name: commands 171 name: feature-flags 207 name: channel-type 215 name: sta-flag-update 219 name: mask 222 name: set 225 name: protocol-features 232 name: nl80211-attrs 233 name [all...] |
H A D | ethtool.yaml | 3 name: ethtool 10 c-family-name: ethtool-genl-name 11 c-version-name: ethtool-genl-version 15 name: udp-tunnel-type 16 enum-name: 19 enum-cnt-name: __ethtool-udp-tunnel-type-cnt 22 name: stringset 27 name: header-flags 29 name [all...] |
H A D | devlink.yaml | 3 name: devlink 12 name: sb-pool-type 15 name: ingress 17 name: egress 20 name: port-type 23 name: notset 25 name: auto 27 name: eth 29 name: ib 32 name [all...] |
H A D | nftables.yaml | 3 name: nftables 12 name: nfgenmsg 16 name: nfgen-family 19 name: version 22 name: res-id 26 name: meta-keys 66 name: bitwise-ops 73 name: cmp-ops 83 name: object-type 98 name [all...] |
/linux/drivers/gpu/drm/msm/registers/display/ |
H A D | hdmi.xml | 13 <domain name="HDMI" width="32"> 14 <enum name="hdmi_hdcp_key_state"> 15 <value name="HDCP_KEYS_STATE_NO_KEYS" value="0"/> 16 <value name="HDCP_KEYS_STATE_NOT_CHECKED" value="1"/> 17 <value name="HDCP_KEYS_STATE_CHECKING" value="2"/> 18 <value name="HDCP_KEYS_STATE_VALID" value="3"/> 19 <value name="HDCP_KEYS_STATE_AKSV_NOT_VALID" value="4"/> 20 <value name="HDCP_KEYS_STATE_CHKSUM_MISMATCH" value="5"/> 21 <value name="HDCP_KEYS_STATE_PROD_AKSV" value="6"/> 22 <value name [all...] |
H A D | mdp5.xml | 9 <domain name="VBIF" width="32"> 12 <domain name="MDP5" width="32"> 14 <enum name="mdp5_intf_type"> 15 <value name="INTF_DISABLED" value="0x0"/> 16 <value name="INTF_DSI" value="0x1"/> 17 <value name="INTF_HDMI" value="0x3"/> 18 <value name="INTF_LCDC" value="0x5"/> 19 <value name="INTF_eDP" value="0x9"/> 20 <value name="INTF_VIRTUAL" value="0x64"/> 22 <value name [all...] |
H A D | dsi_phy_7nm.xml | 7 <domain name="DSI_7nm_PHY_CMN" width="32"> 8 <reg32 offset="0x00000" name="REVISION_ID0"/> 9 <reg32 offset="0x00004" name="REVISION_ID1"/> 10 <reg32 offset="0x00008" name="REVISION_ID2"/> 11 <reg32 offset="0x0000c" name="REVISION_ID3"/> 12 <reg32 offset="0x00010" name="CLK_CFG0"> 13 <bitfield name="DIV_CTRL_3_0" low="0" high="3" type="uint"/> 14 <bitfield name="DIV_CTRL_7_4" low="4" high="7" type="uint"/> 16 <reg32 offset="0x00014" name="CLK_CFG1"> 17 <bitfield name [all...] |
H A D | dsi.xml | 7 <domain name="DSI" width="32"> 8 <enum name="dsi_traffic_mode"> 9 <value name="NON_BURST_SYNCH_PULSE" value="0"/> 10 <value name="NON_BURST_SYNCH_EVENT" value="1"/> 11 <value name="BURST_MODE" value="2"/> 13 <enum name="dsi_vid_dst_format"> 14 <value name="VID_DST_FORMAT_RGB565" value="0"/> 15 <value name="VID_DST_FORMAT_RGB666" value="1"/> 16 <value name="VID_DST_FORMAT_RGB666_LOOSE" value="2"/> 17 <value name [all...] |
H A D | mdp4.xml | 8 <domain name="MDP4" width="32"> 9 <enum name="mdp4_pipe"> 11 <value name="VG1" value="0"/> 12 <value name="VG2" value="1"/> 13 <value name="RGB1" value="2"/> 14 <value name="RGB2" value="3"/> 15 <value name="RGB3" value="4"/> 16 <value name="VG3" value="5"/> 17 <value name="VG4" value="6"/> 20 <enum name [all...] |
H A D | edp.xml | 7 <domain name="EDP" width="32"> 8 <enum name="edp_color_depth"> 9 <value name="EDP_6BIT" value="0"/> 10 <value name="EDP_8BIT" value="1"/> 11 <value name="EDP_10BIT" value="2"/> 12 <value name="EDP_12BIT" value="3"/> 13 <value name="EDP_16BIT" value="4"/> 16 <enum name="edp_component_format"> 17 <value name="EDP_RGB" value="0"/> 18 <value name [all...] |
H A D | dsi_phy_28nm.xml | 7 <domain name="DSI_28nm_PHY" width="32"> 8 <array offset="0x00000" name="LN" length="4" stride="0x40"> 9 <reg32 offset="0x00" name="CFG_0"/> 10 <reg32 offset="0x04" name="CFG_1"/> 11 <reg32 offset="0x08" name="CFG_2"/> 12 <reg32 offset="0x0c" name="CFG_3"/> 13 <reg32 offset="0x10" name="CFG_4"/> 14 <reg32 offset="0x14" name="TEST_DATAPATH"/> 15 <reg32 offset="0x18" name="DEBUG_SEL"/> 16 <reg32 offset="0x1c" name [all...] |