/linux/drivers/media/platform/renesas/vsp1/ |
H A D | vsp1_lut.c | 28 static inline void vsp1_lut_write(struct vsp1_lut *lut, in vsp1_lut_write() argument 40 static int lut_set_table(struct vsp1_lut *lut, struct v4l2_ctrl *ctrl) in lut_set_table() argument 45 dlb = vsp1_dl_body_get(lut->pool); in lut_set_table() 53 spin_lock_irq(&lut->lock); in lut_set_table() 54 swap(lut->lut, dlb); in lut_set_table() 55 spin_unlock_irq(&lut->lock); in lut_set_table() 63 struct vsp1_lut *lut = in lut_s_ctrl() local 68 lut_set_table(lut, ctrl); in lut_s_ctrl() 154 struct vsp1_lut *lut = to_lut(&entity->subdev); in lut_configure_stream() local 156 vsp1_lut_write(lut, dlb, VI6_LUT_CTRL, VI6_LUT_CTRL_EN); in lut_configure_stream() [all …]
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm_color.c | 38 * - Input gamma LUT (de-normalized) 40 * - Surface degamma LUT (normalized) 42 * - Surface regamma LUT (normalized) 51 * The input gamma LUT block isn't really applicable here since it operates 64 * respective property is set to NULL. A linear DGM/RGM LUT should also 108 * degamma TF, shaper TF (before 3D LUT), and blend(dpp.ogam) TF and 330 * __extract_blob_lut - Extracts the DRM lut and lut size from a blob. 332 * @size: lut size 335 * DRM LUT or NULL 345 * __is_lut_linear - check if the given lut is a linear mapping of values [all …]
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/linux/include/drm/ |
H A D | drm_color_mgmt.h | 34 * drm_color_lut_extract - clamp and round LUT entries 36 * @bit_precision: number of bits the hw LUT supports 38 * Extract a degamma/gamma LUT value provided by user (in the form of 64 * drm_color_lut_size - calculate the number of entries in the LUT 65 * @blob: blob containing the LUT 68 * The number of entries in the color LUT stored in @blob. 95 * enum drm_color_lut_tests - hw-specific LUT tests to perform 98 * determine which tests to apply to a userspace-provided LUT. 104 * Checks whether the entries of a LUT all have equal values for the 106 * accepts a single value per LUT entry and assumes that value applies [all …]
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/linux/drivers/gpu/drm/renesas/rcar-du/ |
H A D | rcar_cmm.c | 27 * @lut: 1D-LUT state 28 * @lut.enabled: 1D-LUT enabled flag 32 } lut; member 41 * rcar_cmm_lut_write() - Scale the DRM LUT table entries to hardware precision 44 * @drm_lut: Pointer to the DRM LUT table 66 * disabling and programming of the 1-D LUT unit is supported. 73 * TODO: Add support for LUT double buffer operations to avoid updating the 74 * LUT table entries while a frame is being displayed. 81 /* Disable LUT if no table is provided. */ in rcar_cmm_setup() 82 if (!config->lut.table) { in rcar_cmm_setup() [all …]
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H A D | rcar_cmm.h | 19 * @lut: 1D-LUT configuration 20 * @lut.table: 1D-LUT table entries. Disable LUT operations when NULL 25 } lut; member
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/linux/drivers/gpu/drm/ |
H A D | drm_color_mgmt.c | 44 * Blob property to set the degamma lookup table (LUT) mapping pixel data 47 * Hardware might choose not to use the full precision of the LUT elements 48 * nor use all the elements of the LUT (for example the hardware might 49 * choose to interpolate between LUT[0] and LUT[4]). 59 * hardware). If drivers support multiple LUT sizes then they should 65 * pixel data after the lookup through the degamma LUT and before the 66 * lookup through the gamma LUT. The data is interpreted as a struct 75 * Blob property to set the gamma lookup table (LUT) mapping pixel data 78 * Hardware might choose not to use the full precision of the LUT elements 79 * nor use all the elements of the LUT (for example the hardware might [all …]
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/linux/drivers/video/fbdev/ |
H A D | macfb.c | 58 unsigned char lut; member 64 unsigned char lut; member 73 unsigned char lut; member 79 unsigned char lut; /* OFFSET: 0x10 */ member 101 unsigned char lut; member 106 unsigned char lut; /* TFBClutWDataReg, offset 0x90018 */ member 114 unsigned char lut; member 167 &dafb_cmap_regs->lut); in dafb_setpalette() 170 &dafb_cmap_regs->lut); in dafb_setpalette() 173 &dafb_cmap_regs->lut); in dafb_setpalette() [all …]
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/linux/drivers/gpu/drm/msm/disp/dpu1/ |
H A D | dpu_hw_catalog.c | 609 {.fl = 4, .lut = 0x1b}, 610 {.fl = 5, .lut = 0x5b}, 611 {.fl = 6, .lut = 0x15b}, 612 {.fl = 7, .lut = 0x55b}, 613 {.fl = 8, .lut = 0x155b}, 614 {.fl = 9, .lut = 0x555b}, 615 {.fl = 10, .lut = 0x1555b}, 616 {.fl = 11, .lut = 0x5555b}, 617 {.fl = 12, .lut = 0x15555b}, 618 {.fl = 0, .lut = 0x55555b} [all …]
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H A D | dpu_hw_util.c | 119 u32 *lut[QSEED3_FILTERS] = {NULL, NULL, NULL, NULL, NULL}; in _dpu_hw_setup_scaler3_lut() local 131 lut[0] = scaler3_cfg->dir_lut; in _dpu_hw_setup_scaler3_lut() 137 lut[1] = scaler3_cfg->cir_lut + in _dpu_hw_setup_scaler3_lut() 144 lut[2] = scaler3_cfg->cir_lut + in _dpu_hw_setup_scaler3_lut() 151 lut[3] = scaler3_cfg->sep_lut + in _dpu_hw_setup_scaler3_lut() 158 lut[4] = scaler3_cfg->sep_lut + in _dpu_hw_setup_scaler3_lut() 165 if (!lut[filter]) in _dpu_hw_setup_scaler3_lut() 175 (lut[filter])[lut_offset++]); in _dpu_hw_setup_scaler3_lut() 194 u32 *lut[QSEED3LITE_FILTERS] = {NULL, NULL}; in _dpu_hw_setup_scaler3lite_lut() local 206 lut[0] = scaler3_cfg->sep_lut + in _dpu_hw_setup_scaler3lite_lut() [all …]
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/linux/drivers/gpu/drm/nouveau/dispnv50/ |
H A D | lut.c | 22 #include "lut.h" 32 nv50_lut_load(struct nv50_lut *lut, int buffer, struct drm_property_blob *blob, in nv50_lut_load() argument 36 void __iomem *mem = lut->mem[buffer].object.map.ptr; in nv50_lut_load() 37 const u32 addr = lut->mem[buffer].addr; in nv50_lut_load() 59 nv50_lut_fini(struct nv50_lut *lut) in nv50_lut_fini() argument 62 for (i = 0; i < ARRAY_SIZE(lut->mem); i++) in nv50_lut_fini() 63 nvif_mem_dtor(&lut->mem[i]); in nv50_lut_fini() 68 struct nv50_lut *lut) in nv50_lut_init() argument 72 for (i = 0; i < ARRAY_SIZE(lut->mem); i++) { in nv50_lut_init() 74 size * 8, &lut->mem[i]); in nv50_lut_init()
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/linux/drivers/staging/media/atomisp/pci/isp/kernels/bnlm/ |
H A D | ia_css_bnlm.host.c | 30 * lut : bnlm_lut struct containing encoded vmem parameters look-up table 31 * lut_thr : array containing threshold values for lut 36 bnlm_lut_encode(struct bnlm_lut *lut, const int32_t *lut_thr, in bnlm_lut_encode() argument 45 * Min size of the LUT is 2 entries. in bnlm_lut_encode() 47 * Max size of the LUT is 16 entries, so that the LUT can fit into a in bnlm_lut_encode() 50 * vector. If the LUT size is less than 16, then remaining elements are in bnlm_lut_encode() 62 lut->thr[0][i] = 0; in bnlm_lut_encode() 63 lut->val[0][i] = 0; in bnlm_lut_encode() 68 lut->thr[0][i] = lut_thr[i]; in bnlm_lut_encode() 69 lut->val[0][i] = lut_val[i]; in bnlm_lut_encode() [all …]
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/linux/drivers/gpu/drm/i915/display/ |
H A D | intel_color.c | 183 static bool lut_is_legacy(const struct drm_property_blob *lut) in lut_is_legacy() argument 185 return lut && drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; in lut_is_legacy() 536 * On GLK both pipe CSC and degamma LUT are controlled in ilk_assign_csc() 538 * LUT is needed but CSC is not we need to load an in ilk_assign_csc() 808 /* convert hw value with given bit_precision to lut property val */ 1178 struct drm_color_lut *lut; in create_linear_lut() local 1182 sizeof(lut[0]) * lut_size, in create_linear_lut() 1187 lut = blob->data; in create_linear_lut() 1192 lut[i].red = val; in create_linear_lut() 1193 lut[i].green = val; in create_linear_lut() [all …]
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/linux/drivers/gpio/ |
H A D | gpio-adp5520.c | 19 unsigned char lut[ADP5520_MAXGPIOS]; member 40 return !!(reg_val & dev->lut[off]); in adp5520_gpio_get_value() 51 dev->lut[off]); in adp5520_gpio_set_value() 54 dev->lut[off]); in adp5520_gpio_set_value() 65 dev->lut[off]); in adp5520_gpio_direction_input() 79 dev->lut[off]); in adp5520_gpio_direction_output() 82 dev->lut[off]); in adp5520_gpio_direction_output() 85 dev->lut[off]); in adp5520_gpio_direction_output() 116 dev->lut[gpios++] = 1 << i; in adp5520_gpio_probe()
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/linux/drivers/net/ethernet/aquantia/atlantic/macsec/ |
H A D | MSS_Ingress_registers.h | 50 * (IGPRCTLF) LUT 51 * 0x1 : Ingress Pre-Security Classification LUT (IGPRC) 52 * 0x2 : Ingress Packet Format (IGPFMT) SAKey LUT 53 * 0x3 : Ingress Packet Format (IGPFMT) SC/SA LUT 54 * 0x4 : Ingress Post-Security Classification LUT 57 * (IGPOCTLF) LUT
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H A D | MSS_Egress_registers.h | 51 /* 0x0 : Egress MAC Control FIlter (CTLF) LUT 52 * 0x1 : Egress Classification LUT 53 * 0x2 : Egress SC/SA LUT
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/linux/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/ |
H A D | input_formatter_local.h | 32 * The switch LUT's coding defines a sink for each 37 * LUT[0,1] channel=0, format type {0,1,...31} 38 * LUT[2,3] channel=1, format type {0,1,...31} 39 * LUT[4,5] channel=2, format type {0,1,...31} 40 * LUT[6,7] channel=3, format type {0,1,...31} 49 * a channel to a sink. At that point the LUT's belonging to
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H A D | gdc.c | 56 * Input LUT format: 59 * Output LUT format (interleaved): 64 * to program gdc LUT registers. This makes it difficult to do piecemeal 68 * gdc LUT registers.
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/linux/drivers/gpu/drm/amd/display/dc/core/ |
H A D | dc_surface.c | 243 struct dc_3dlut *lut = container_of(kref, struct dc_3dlut, refcount); in dc_3dlut_func_free() local 245 kvfree(lut); in dc_3dlut_func_free() 250 struct dc_3dlut *lut = kvzalloc(sizeof(*lut), GFP_KERNEL); in dc_create_3dlut_func() local 252 if (lut == NULL) in dc_create_3dlut_func() 255 kref_init(&lut->refcount); in dc_create_3dlut_func() 256 lut->state.raw = 0; in dc_create_3dlut_func() 258 return lut; in dc_create_3dlut_func() 265 void dc_3dlut_func_release(struct dc_3dlut *lut) in dc_3dlut_func_release() argument 267 kref_put(&lut->refcount, dc_3dlut_func_free); in dc_3dlut_func_release() 270 void dc_3dlut_func_retain(struct dc_3dlut *lut) in dc_3dlut_func_retain() argument [all …]
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/linux/drivers/clk/rockchip/ |
H A D | softrst.c | 15 const int *lut; member 31 if (softrst->lut) in rockchip_softrst_assert() 32 id = softrst->lut[id]; in rockchip_softrst_assert() 63 if (softrst->lut) in rockchip_softrst_deassert() 64 id = softrst->lut[id]; in rockchip_softrst_deassert() 106 softrst->lut = lookup_table; in rockchip_register_softrst_lut()
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/linux/drivers/net/ethernet/intel/iavf/ |
H A D | iavf_common.c | 259 * @lut: pointer to the lut buffer provided by the caller 260 * @lut_size: size of the lut buffer 267 u8 *lut, u16 lut_size, in iavf_aq_get_set_rss_lut() argument 301 status = iavf_asq_send_command(hw, &desc, lut, lut_size, NULL); in iavf_aq_get_set_rss_lut() 311 * @lut: pointer to the lut buffer provided by the caller 312 * @lut_size: size of the lut buffer 317 bool pf_lut, u8 *lut, u16 lut_size) in iavf_aq_set_rss_lut() argument 319 return iavf_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); in iavf_aq_set_rss_lut()
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/linux/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/ |
H A D | gdc_public.h | 20 - The LUT should not be partially written 21 - The LUT format is a quadri-phase interpolation 26 \return none, GDC[ID].lut[0...3][0...HRT_GDC_N-1] = data
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
H A D | mpc.h | 33 * 3D LUT. 726 * Power on/off memory LUT for given MPCC. 727 * Powering on enables LUT to be updated. 848 * - [in] params - curve parameters for the LUT configuration 851 …* bool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled… 870 …* bool - wheter shaper was set (set with given parameters) or not (params is NULL and LUT is disab… 900 * - [in] params - tetrahedral parameters for the LUT configuration 903 …* bool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled… 994 * Update 3D LUT fast load select. 1011 * Populate LUT with given tetrahedral parameters. [all …]
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/linux/drivers/accel/amdxdna/ |
H A D | aie2_error.c | 149 const struct aie_event_category *lut; in aie_get_error_category() local 155 lut = aie_ml_shim_tile_event_cat; in aie_get_error_category() 159 lut = aie_ml_core_event_cat; in aie_get_error_category() 164 lut = aie_ml_mem_tile_event_cat; in aie_get_error_category() 167 lut = aie_ml_mem_event_cat; in aie_get_error_category() 176 if (event_id != lut[i].event_id) in aie_get_error_category() 179 return lut[i].category; in aie_get_error_category()
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/linux/drivers/gpu/drm/arm/ |
H A D | malidp_crtc.c | 130 struct drm_color_lut *lut = (struct drm_color_lut *)lut_blob->data; in malidp_generate_gamma_table() local 138 out_start = drm_color_lut_extract(lut[segments[i].start].green, in malidp_generate_gamma_table() 140 out_end = drm_color_lut_extract(lut[segments[i].end].green, 12); in malidp_generate_gamma_table() 148 * Check if there is a new gamma LUT and if it is of an acceptable size. Also, 155 struct drm_color_lut *lut; in malidp_crtc_atomic_check_gamma() local 173 lut = (struct drm_color_lut *)state->gamma_lut->data; in malidp_crtc_atomic_check_gamma() 175 if (!((lut[i].red == lut[i].green) && in malidp_crtc_atomic_check_gamma() 176 (lut[i].red == lut[i].blue))) in malidp_crtc_atomic_check_gamma() 186 * changing the gamma LUT doesn't depend on any external in malidp_crtc_atomic_check_gamma()
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/linux/Documentation/devicetree/bindings/display/msm/ |
H A D | qcom,sm6115-dpu.yaml | 33 - description: Display lut 42 - const: lut 73 clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
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