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Searched full:ld1 (Results 1 – 9 of 9) sorted by relevance

/qemu/tests/tcg/aarch64/
H A Dtest-aes.c8 asm("ld1 { v0.16b }, [%1]\n\t" in test_SB_SR()
18 asm("ld1 { v0.16b }, [%1]\n\t" in test_MC()
33 asm("ld1 { v0.16b }, [%1]\n\t" in test_ISB_ISR()
43 asm("ld1 { v0.16b }, [%1]\n\t" in test_IMC()
/qemu/target/arm/tcg/
H A Dsve_ldst_internal.h88 DO_LD_HOST(ld1##NAME##_be, H, TE, TM, LD##_be_p) \
89 DO_LD_HOST(ld1##NAME##_le, H, TE, TM, LD##_le_p) \
90 DO_LD_TLB(ld1##NAME##_be, H, TE, TM, cpu_##LD##_be_data_ra) \
91 DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra)
H A Dtranslate-sve.c4878 * For consistency, do this even for LD1. in do_ldrq()
/qemu/target/hexagon/imported/
H A Dencode_subinsn.def25 /* Ld1-type subinsns */
119 /* NCJ goes with LD1, LD2 */
H A Dsubinsns.idef61 /* Ld1/2 subinsns */
/qemu/hw/net/
H A Digb.c272 /* PCIe Init. Conf 1,2,3 |PCICtrl| LD1,3 |DDevID |DevRev | LD0,2 */
276 /*---------------| LD1,3 | LD0,2 | ROEnd | ROSta | Wdog | VPD */
H A De1000e.c253 /* PCIe Init. Conf 1,2,3 |PCICtrl|PHY|LD1|-------| RevID | LD0,2 */
/qemu/tcg/mips/
H A Dtcg-target.c.inc1338 const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR;
1375 tcg_out_opc_imm(s, ld1, lo, base, 0);
/qemu/disas/
H A Dm68k.c3716 {"mulsl", 4, two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32 },
3721 {"mulul", 4, two(0046000,000000), two(0177700,0107770), ";lD1", m68020up|cpu32 },