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/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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H A Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
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/linux/arch/powerpc/boot/dts/
H A Dmicrowatt.dts1 /dts-v1/;
2 #include <dt-bindings/gpio/gpio.h>
5 #size-cells = <0x02>;
6 #address-cells = <0x02>;
8 compatible = "microwatt-soc";
15 reserved-memory {
16 #size-cells = <0x02>;
17 #address-cells = <0x02>;
28 #clock-cells = <0>;
29 compatible = "fixed-clock";
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/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
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/linux/kernel/dma/
H A Dswiotlb.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * I/O TLBs (aka DMA address translation hardware).
9 * Copyright (C) 2000, 2003 Hewlett-Packard Co
10 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API.
14 * unnecessary i-cache flushing.
21 #define pr_fmt(fmt) "software IO TLB: " fmt
27 #include <linux/dma-direct.h>
28 #include <linux/dma-map-ops.h>
33 #include <linux/iommu-helper.h>
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/linux/arch/riscv/boot/dts/starfive/
H A Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
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H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/linux/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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/linux/arch/powerpc/mm/book3s64/
H A Dhash_tlb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * TLB and MMU hash table.
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
25 #include <asm/tlb.h>
27 #include <asm/pte-walk.h>
49 int i, offset; in hpte_need_flush() local
51 i = batch->index; in hpte_need_flush()
54 * Get page size (maybe move back to caller). in hpte_need_flush()
57 * for SPEs, we obtain the page size from the slice, which thus in hpte_need_flush()
64 /* Mask the address for the correct page size */ in hpte_need_flush()
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H A Dhash_native.c1 // SPDX-License-Identifier: GPL-2.0-or-later
23 #include <asm/tlb.h>
27 #include <asm/ppc-opcode.h>
28 #include <asm/feature-fixups.h>
93 va &= ~((1ul << (64 - 52)) - 1); in ___tlbie()
98 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) in ___tlbie()
102 /* We need 14 to 14 + i bits of va */ in ___tlbie()
104 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1); in ___tlbie()
117 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) in ___tlbie()
140 * re-order the tlbie in fixup_tlbie_vpn()
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H A Dradix_tlb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TLB flush routines for radix kernels.
5 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
15 #include <asm/ppc-opcode.h>
16 #include <asm/tlb.h>
26 * i.e., r=1 and is=01 or is=10 or is=11
39 : : "r"(rb), "r"(rs), "i"(ric), "i"(prs) in tlbiel_radix_set_isa300()
50 * Flush the first set of the TLB, and the entire Page Walk Cache in tlbiel_all_isa300()
52 * TLB. in tlbiel_all_isa300()
95 WARN(1, "%s called on pre-POWER9 CPU\n", __func__); in radix__tlbiel_all()
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/linux/arch/powerpc/mm/nohash/
H A D44x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * -- paulus
11 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
27 #include <asm/text-patching.h>
32 /* Used by the 44x TLB replacement exception handler.
36 unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
43 /* The TLB miss handlers hard codes the watermark in a cmpli in ppc44x_update_tlb_hwater()
46 * in the 2 TLB miss handlers when updating the value in ppc44x_update_tlb_hwater()
53 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 44x type MMU
57 unsigned int entry = tlb_44x_hwater--; in ppc44x_pin_tlb()
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/linux/arch/nios2/kernel/
H A Dcpuinfo.c1 // SPDX-License-Identifier: GPL-2.0-or-later
41 if (!of_property_read_bool(cpu, "altr,has-initda")) in setup_cpuinfo()
43 "hardware system to have more than 4-byte line data " in setup_cpuinfo()
46 cpuinfo.cpu_clock_freq = fcpu(cpu, "clock-frequency"); in setup_cpuinfo()
51 cpuinfo.has_div = of_property_read_bool(cpu, "altr,has-div"); in setup_cpuinfo()
52 cpuinfo.has_mul = of_property_read_bool(cpu, "altr,has-mul"); in setup_cpuinfo()
53 cpuinfo.has_mulx = of_property_read_bool(cpu, "altr,has-mulx"); in setup_cpuinfo()
54 cpuinfo.has_bmx = of_property_read_bool(cpu, "altr,has-bmx"); in setup_cpuinfo()
55 cpuinfo.has_cdx = of_property_read_bool(cpu, "altr,has-cdx"); in setup_cpuinfo()
56 cpuinfo.mmu = of_property_read_bool(cpu, "altr,has-mmu"); in setup_cpuinfo()
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/linux/drivers/parisc/
H A Dccio-dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 ** ccio-dma.c:
4 ** DMA management routines for first generation cache-coherent machines.
5 ** Program U2/Uturn in "Virtual Mode" and use the I/O MMU.
9 ** (c) Copyright 2000 Hewlett-Packard Company
13 ** the I/O MMU - basically what x86 does.
16 ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).
17 ** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute.
19 ** o Doesn't work under PCX-U/U+ machines since they didn't follow
20 ** the coherency design originally worked out. Only PCX-W does.
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/linux/arch/parisc/kernel/
H A Dcache.c6 * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
10 * Cache and TLB management
55 void flush_data_cache_local(void *); /* flushes local data-cache only */
56 void flush_instruction_cache_local(void); /* flushes local code-cache only */
60 /* On some machines (i.e., ones with the Merced bus), there can be
62 * by software. We need a spinlock around all TLB flushes to ensure
125 test_bit(PG_dcache_dirty, &folio->flags)) { in __update_cache()
126 while (nr--) in __update_cache()
128 clear_bit(PG_dcache_dirty, &folio->flags); in __update_cache()
130 while (nr--) in __update_cache()
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/linux/arch/microblaze/include/asm/
H A Dmmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2008-2009 PetaLogix
27 unsigned long w:1; /* Write-thru cache mode */
28 unsigned long i:1; /* Cache inhibited */ member
43 unsigned long t:1; /* Normal or I/O type */
46 unsigned long n:1; /* No-execute */
51 extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
52 extern void _tlbia(void); /* invalidate all TLB entries */
55 * tlb_skip size stores actual number skipped TLBs from TLB0 - every directy TLB
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/linux/arch/powerpc/include/asm/nohash/32/
H A Dpte-44x.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * Because of the 3 word TLB entries to support 36-bit addressing,
11 * are easily loaded during exception processing. I decided to
14 * in as sensibly as they can be in the area below a 4KB page size
16 * ERPN fields in the TLB. -Matt
19 * easier to move into the TLB from the PTE. -BenH.
21 * Note that these bits preclude future use of a page size
25 * PPC 440 core has following TLB attribute fields;
29 * RPN................................. - - - - - - ERPN.......
33 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
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/linux/arch/parisc/include/uapi/asm/
H A Dpdc.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 #define PDC_BAD_PROC -1 /* Called non-existent procedure*/
15 #define PDC_BAD_OPTION -2 /* Called with non-existent option */
16 #define PDC_ERROR -3 /* Call could not complete without an error */
17 #define PDC_NE_MOD -5 /* Module not found */
18 #define PDC_NE_CELL_MOD -7 /* Cell module not found */
19 #define PDC_NE_BOOTDEV -9 /* Cannot locate a console device or boot device */
20 #define PDC_INVALID_ARG -10 /* Called with an invalid argument */
21 #define PDC_BUS_POW_WARN -12 /* Call could not complete in allowed power budget */
22 #define PDC_NOT_NARROW -17 /* Narrow mode not supported */
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/linux/arch/alpha/kernel/
H A Dpci_iommu.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/dma-map-ops.h>
15 #include <linux/iommu-helper.h>
44 return (paddr >> (PAGE_SHIFT-1)) | 1; in mk_iommu_pte()
68 /* Note that the TLB lookup logic uses bitwise concatenation, in iommu_arena_new_node()
70 the size of the window. Retain the align parameter so that in iommu_arena_new_node()
71 particular systems can over-align the arena. */ in iommu_arena_new_node()
76 arena->ptes = memblock_alloc_or_panic(mem_size, align); in iommu_arena_new_node()
78 spin_lock_init(&arena->lock); in iommu_arena_new_node()
79 arena->hose = hose; in iommu_arena_new_node()
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/linux/arch/x86/mm/
H A Dpgtable.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <asm/tlb.h>
11 phys_addr_t physical_mask __ro_after_init = (1ULL << __PHYSICAL_MASK_SHIFT) - 1;
21 void ___pte_free_tlb(struct mmu_gather *tlb, struct page *pte) in ___pte_free_tlb() argument
24 tlb_remove_ptdesc(tlb, page_ptdesc(pte)); in ___pte_free_tlb()
28 void ___pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd) in ___pmd_free_tlb() argument
32 * NOTE! For PAE, any changes to the top page-directory-pointer-table in ___pmd_free_tlb()
36 tlb->need_flush_all = 1; in ___pmd_free_tlb()
38 tlb_remove_ptdesc(tlb, virt_to_ptdesc(pmd)); in ___pmd_free_tlb()
42 void ___pud_free_tlb(struct mmu_gather *tlb, pud_t *pud) in ___pud_free_tlb() argument
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/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dpipeline.json10 "BriefDescription": "Number of I-ERAT reloads"
25 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued…
35 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ…
40 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl…
80 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
95 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
110 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K"
115 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispa…
120 …"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) and 1G (radi…
160 …"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data fro…
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/linux/arch/sparc/kernel/
H A Dtsb.S1 /* SPDX-License-Identifier: GPL-2.0 */
17 /* Invoked from TLB miss handler, we are in the
23 * %g3: FAULT_CODE_{D,I}TLB
46 * %g1 -- PAGE_SIZE TSB entry address
47 * %g3 -- FAULT_CODE_{D,I}TLB
48 * %g4 -- missing virtual address
49 * %g6 -- TAG TARGET (vaddr >> 22)
67 cmp %g5, -1
106 * %g1 -- TSB entry address
107 * %g3 -- FAULT_CODE_{D,I}TLB
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/linux/arch/arc/mm/
H A Dtlbex.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * TLB Exception Handling for ARC
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -MMU v1: moved out legacy code into a separate file
9 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
13 * -For MMU V2, we need not do heuristics at the time of committing a D-TLB
14 * entry, so that it doesn't knock out its I-TLB entry
15 * -Some more fine tuning:
19 * -Practically rewrote the I/D TLB Miss handlers
26 * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
[all …]
/linux/drivers/gpu/drm/msm/
H A Dmsm_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
8 #include <linux/io-pgtable.h>
29 const struct iommu_flush_ops *tlb; member
46 size_t size, size_t *count) in calc_pgsize() argument
53 /* Page sizes supported by the hardware and small enough for @size */ in calc_pgsize()
54 pgsizes = pagetable->pgsize_bitmap & GENMASK(__fls(size), 0); in calc_pgsize()
60 /* Make sure we have at least one suitable page size */ in calc_pgsize()
63 /* Pick the biggest page size remaining */ in calc_pgsize()
69 /* Find the next biggest support page size, if it exists */ in calc_pgsize()
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/linux/arch/arm64/kvm/
H A Dnested.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 - Columbia University and Linaro Ltd.
28 /* -1 when not mapped on a CPU */
32 * true if the TLB is valid. Can only be changed with the
39 * Ratio of live shadow S2 MMU per vcpu. This is a trade-off between
48 kvm->arch.nested_mmus = NULL; in kvm_init_nested()
49 kvm->arch.nested_mmus_size = 0; in kvm_init_nested()
50 atomic_set(&kvm->arch.vncr_map_count, 0); in kvm_init_nested()
70 struct kvm *kvm = vcpu->kvm; in kvm_vcpu_init_nested()
74 if (test_bit(KVM_ARM_VCPU_HAS_EL2_E2H0, kvm->arch.vcpu_features) && in kvm_vcpu_init_nested()
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