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/linux/drivers/gpu/host1x/
H A Ddev.h33 int (*init)(struct host1x_channel *channel, struct host1x *host,
56 void (*show_channel_cdma)(struct host1x *host,
59 void (*show_channel_fifo)(struct host1x *host,
62 void (*show_mlocks)(struct host1x *host, struct output *output);
74 void (*enable_protection)(struct host1x *host);
78 int (*init_host_sync)(struct host1x *host, u32 cpm);
80 struct host1x *host, unsigned int id, u32 thresh);
81 void (*enable_syncpt_intr)(struct host1x *host, unsigned int id);
82 void (*disable_syncpt_intr)(struct host1x *host, unsigned int id);
83 void (*disable_all_syncpt_intrs)(struct host1x *hos
129 struct host1x { global() struct
130 infohost1x global() argument
137 syncpthost1x global() argument
138 baseshost1x global() argument
151 syncpt_ophost1x global() argument
152 intr_ophost1x global() argument
153 channel_ophost1x global() argument
154 cdma_ophost1x global() argument
155 cdma_pb_ophost1x global() argument
156 debug_ophost1x global() argument
158 nop_sphost1x global() argument
162 channel_listhost1x global() argument
163 context_listhost1x global() argument
174 cachehost1x global() argument
177 dma_parmshost1x global() argument
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H A Dintr.h3 * Tegra host1x Interrupt Management
11 struct host1x;
15 struct host1x *host;
19 /* Initialize host1x sync point interrupt */
20 int host1x_intr_init(struct host1x *host);
22 /* Deinitialize host1x sync point interrupt */
23 void host1x_intr_deinit(struct host1x *host);
25 /* Enable host1x sync point interrupt */
26 void host1x_intr_start(struct host1x *host);
28 /* Disable host1x syn
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H A Ddebug.c54 struct host1x *m = dev_get_drvdata(ch->dev->parent); in show_channel()
78 static void show_syncpts(struct host1x *m, struct output *o, bool show_all) in show_syncpts()
126 static void show_all(struct host1x *m, struct output *o, bool show_fifo) in show_all()
170 static void host1x_debugfs_init(struct host1x *host1x) in host1x_debugfs_init() argument
172 struct dentry *de = debugfs_create_dir("tegra-host1x", NULL); in host1x_debugfs_init()
175 host1x->debugfs = de; in host1x_debugfs_init()
177 debugfs_create_file("status", S_IRUGO, de, host1x, &host1x_debug_fops); in host1x_debugfs_init()
178 debugfs_create_file("status_all", S_IRUGO, de, host1x, in host1x_debugfs_init()
184 host1x_hw_debug_init(host1x, d in host1x_debugfs_init()
194 host1x_debugfs_exit(struct host1x * host1x) host1x_debugfs_exit() argument
199 host1x_debug_init(struct host1x * host1x) host1x_debug_init() argument
205 host1x_debug_deinit(struct host1x * host1x) host1x_debug_deinit() argument
211 host1x_debug_dump(struct host1x * host1x) host1x_debug_dump() argument
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H A Dcdma.c3 * Tegra host1x Command DMA
12 #include <linux/host1x.h>
17 #include <trace/events/host1x.h>
51 struct host1x *host1x = cdma_to_host1x(cdma); in host1x_pushbuffer_destroy() local
56 if (host1x->domain) { in host1x_pushbuffer_destroy()
57 iommu_unmap(host1x->domain, pb->dma, pb->alloc_size); in host1x_pushbuffer_destroy()
58 free_iova(&host1x->iova, iova_pfn(&host1x->iova, pb->dma)); in host1x_pushbuffer_destroy()
61 dma_free_wc(host1x in host1x_pushbuffer_destroy()
73 struct host1x *host1x = cdma_to_host1x(cdma); host1x_pushbuffer_init() local
235 host1x_cdma_wait_pushbuffer_space(struct host1x * host1x,struct host1x_cdma * cdma,unsigned int needed) host1x_cdma_wait_pushbuffer_space() argument
364 struct host1x *host1x = cdma_to_host1x(cdma); host1x_cdma_update_sync_queue() local
530 struct host1x *host1x = cdma_to_host1x(cdma); host1x_cdma_deinit() local
548 struct host1x *host1x = cdma_to_host1x(cdma); host1x_cdma_begin() local
621 struct host1x *host1x = cdma_to_host1x(cdma); host1x_cdma_push_wide() local
663 struct host1x *host1x = cdma_to_host1x(cdma); host1x_cdma_end() local
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H A Dsyncpt.c3 * Tegra host1x Syncpoints
13 #include <trace/events/host1x.h>
24 host1x_syncpt_base_request(struct host1x *host) in host1x_syncpt_base_request()
48 * @host: host1x device data
58 struct host1x_syncpt *host1x_syncpt_alloc(struct host1x *host, in host1x_syncpt_alloc()
110 * @sp: host1x syncpoint
124 * @sp: host1x syncpoint
136 void host1x_syncpt_restore(struct host1x *host) in host1x_syncpt_restore()
163 void host1x_syncpt_save(struct host1x *host) in host1x_syncpt_save()
205 * @sp: host1x syncpoin
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H A Dsyncpt.h3 * Tegra host1x Syncpoints
12 #include <linux/host1x.h>
20 struct host1x;
39 struct host1x *host;
54 int host1x_syncpt_init(struct host1x *host);
57 void host1x_syncpt_deinit(struct host1x *host);
60 unsigned int host1x_syncpt_nb_pts(struct host1x *host);
63 unsigned int host1x_syncpt_nb_bases(struct host1x *host);
66 unsigned int host1x_syncpt_nb_mlocks(struct host1x *host);
108 /* Save host1x syn
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H A Ddev.c3 * Tegra host1x driver
23 #include <trace/events/host1x.h>
45 void host1x_common_writel(struct host1x *host1x, u32 v, u32 r) in host1x_common_writel() argument
47 writel(v, host1x->common_regs + r); in host1x_common_writel()
50 void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r) in host1x_hypervisor_writel() argument
52 writel(v, host1x->hv_regs + r); in host1x_hypervisor_writel()
55 u32 host1x_hypervisor_readl(struct host1x *host1x, u3 argument
60 host1x_sync_writel(struct host1x * host1x,u32 v,u32 r) host1x_sync_writel() argument
67 host1x_sync_readl(struct host1x * host1x,u32 r) host1x_sync_readl() argument
325 host1x_wants_iommu(struct host1x * host1x) host1x_wants_iommu() argument
818 host1x_get_dma_mask(struct host1x * host1x) host1x_get_dma_mask() argument
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H A Dcontext.c21 int host1x_memory_context_list_init(struct host1x *host1x) in host1x_memory_context_list_init() argument
23 struct host1x_memory_context_list *cdl = &host1x->context_list; in host1x_memory_context_list_init()
24 struct device_node *node = host1x->dev->of_node; in host1x_memory_context_list_init()
45 ctx->host = host1x; in host1x_memory_context_list_init()
56 dev_set_name(&ctx->dev, "host1x-ctx.%d", i); in host1x_memory_context_list_init()
58 ctx->dev.parent = host1x->dev; in host1x_memory_context_list_init()
66 dev_err(host1x->dev, "could not add context device %d: %d\n", i, err); in host1x_memory_context_list_init()
73 dev_err(host1x->dev, "IOMMU configuration failed for context device %d: %d\n", in host1x_memory_context_list_init()
81 dev_err(host1x in host1x_memory_context_list_init()
119 host1x_memory_context_alloc(struct host1x * host1x,struct device * dev,struct pid * pid) host1x_memory_context_alloc() argument
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H A Ddebug.h3 * Tegra host1x Debug
13 struct host1x;
41 void host1x_debug_init(struct host1x *host1x);
42 void host1x_debug_deinit(struct host1x *host1x);
43 void host1x_debug_dump(struct host1x *host1x);
H A Dchannel.c3 * Tegra host1x Channel
15 /* Constructor for the host1x device list */
43 struct host1x *host = dev_get_drvdata(job->channel->dev->parent); in host1x_job_submit()
59 * @host: Host1x device object
65 struct host1x_channel *host1x_channel_get_index(struct host1x *host, in host1x_channel_get_index()
78 struct host1x *host = dev_get_drvdata(channel->dev->parent); in host1x_channel_stop()
86 * @host: host1x instance
90 void host1x_channel_stop_all(struct host1x *host) in host1x_channel_stop_all()
107 struct host1x *host = dev_get_drvdata(channel->dev->parent); in release_channel()
122 static struct host1x_channel *acquire_unused_channel(struct host1x *hos
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H A DKconfig7 tristate "NVIDIA Tegra host1x driver"
13 Driver for the NVIDIA Tegra host1x hardware.
15 The Tegra host1x module is the DMA engine for register access to
17 by host1x are referred to as clients. host1x includes some other
23 bool "Enable HOST1X security firewall"
H A Dcontext.h3 * Host1x context devices
14 struct host1x;
25 int host1x_memory_context_list_init(struct host1x *host1x);
28 static inline int host1x_memory_context_list_init(struct host1x *host1x) in host1x_memory_context_list_init() argument
H A Dintr.c3 * Tegra host1x Interrupt Management
31 static void host1x_intr_update_hw_state(struct host1x *host, struct host1x_syncpt *sp) in host1x_intr_update_hw_state()
45 void host1x_intr_add_fence_locked(struct host1x *host, struct host1x_syncpt_fence *fence) in host1x_intr_add_fence_locked()
55 bool host1x_intr_remove_fence(struct host1x *host, struct host1x_syncpt_fence *fence) in host1x_intr_remove_fence()
75 void host1x_intr_handle_interrupt(struct host1x *host, unsigned int id) in host1x_intr_handle_interrupt()
101 int host1x_intr_init(struct host1x *host) in host1x_intr_init()
134 void host1x_intr_deinit(struct host1x *host) in host1x_intr_deinit()
138 void host1x_intr_start(struct host1x *host) in host1x_intr_start()
152 void host1x_intr_stop(struct host1x *host) in host1x_intr_stop()
H A Dchannel.h3 * Tegra host1x Channel
17 struct host1x;
41 struct host1x_channel *host1x_channel_get_index(struct host1x *host,
43 void host1x_channel_stop_all(struct host1x *host);
/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-host1x.yaml4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
7 title: NVIDIA Tegra host1x controller
13 description: The host1x top-level node defines a number of children, each
14 representing one of the host1x client modules defined in this binding.
20 - nvidia,tegra20-host1x
21 - nvidia,tegra30-host1x
22 - nvidia,tegra114-host1x
23 - nvidia,tegra124-host1x
24 - nvidia,tegra210-host1x
25 - nvidia,tegra186-host1x
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/linux/include/linux/
H A Dhost1x.h30 struct host1x;
34 u64 host1x_get_dma_mask(struct host1x *host1x);
37 * struct host1x_bo_cache - host1x buffer object cache
64 * struct host1x_client_ops - host1x client operations
65 * @early_init: host1x client early initialization code
66 * @init: host1x client initialization code
67 * @exit: host1x client tear down code
68 * @late_exit: host1x client late tear down code
69 * @suspend: host1x clien
487 host1x_memory_context_alloc(struct host1x * host1x,struct device * dev,struct pid * pid) host1x_memory_context_alloc() argument
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/linux/drivers/gpu/host1x/hw/
H A Dcdma_hw.c3 * Tegra host1x Command DMA
91 struct host1x *host1x = cdma_to_host1x(cdma); in cdma_timeout_restart() local
123 dev_dbg(host1x->dev, in cdma_timeout_restart()
170 static void cdma_hw_cmdproc_stop(struct host1x *host, struct host1x_channel *ch, in cdma_hw_cmdproc_stop()
185 static void cdma_hw_teardown(struct host1x *host, struct host1x_channel *ch) in cdma_hw_teardown()
200 struct host1x *host = cdma_to_host1x(cdma); in cdma_freeze()
228 struct host1x *host1x = cdma_to_host1x(cdma); in cdma_resume() local
231 dev_dbg(host1x in cdma_resume()
253 struct host1x *host1x = cdma_to_host1x(cdma); timeout_release_mlock() local
293 struct host1x *host1x; cdma_timeout_handler() local
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H A Dsyncpt_hw.c3 * Tegra host1x Syncpoints
19 struct host1x *host = sp->host; in syncpt_restore()
30 struct host1x *host = sp->host; in syncpt_restore_wait_base()
43 struct host1x *host = sp->host; in syncpt_read_wait_base()
55 struct host1x *host = sp->host; in syncpt_load()
78 struct host1x *host = sp->host; in syncpt_cpu_incr()
107 struct host1x *host = sp->host; in syncpt_assign_to_channel()
117 * @host: host1x instance
122 static void syncpt_enable_protection(struct host1x *host) in syncpt_enable_protection()
H A Dintr_hw.c3 * Tegra host1x Interrupt Management
17 struct host1x *host = irq_data->host; in syncpt_thresh_isr()
38 static void host1x_intr_disable_all_syncpt_intrs(struct host1x *host) in host1x_intr_disable_all_syncpt_intrs()
51 host1x_intr_init_host_sync(struct host1x *host, u32 cpm) in host1x_intr_init_host_sync()
86 static void host1x_intr_set_syncpt_threshold(struct host1x *host, in host1x_intr_set_syncpt_threshold()
93 static void host1x_intr_enable_syncpt_intr(struct host1x *host, in host1x_intr_enable_syncpt_intr()
100 static void host1x_intr_disable_syncpt_intr(struct host1x *host, in host1x_intr_disable_syncpt_intr()
H A Dhost1x02.h3 * Host1x init for Tegra114 SoCs
11 struct host1x;
13 int host1x02_init(struct host1x *host);
H A Dhost1x08.h3 * Host1x init for Tegra234 SoCs
11 struct host1x;
13 int host1x08_init(struct host1x *host);
/linux/Documentation/gpu/
H A Dtegra.rst6 the host1x controller. host1x supplies command streams, gathered from a push
18 - A host1x driver that provides infrastructure and access to the host1x
25 GPU and video engines via host1x.
30 The various host1x clients need to be bound together into a logical device in
32 this is implemented in the host1x driver. When a driver is registered with the
37 to the logical host1x device.
47 Host1x Infrastructure Reference
50 .. kernel-doc:: include/linux/host1x
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/linux/Documentation/devicetree/bindings/gpu/host1x/
H A Dnvidia,tegra210-nvdec.yaml4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#
11 and newer chips. It is located on the Host1x bus and typically
12 programmed through Host1x channels.
65 nvidia,host1x-class:
67 Host1x class of the engine, used to specify the targeted engine
68 when programming the engine through Host1x channels or when
69 configuring engine-specific behavior in Host1x.
H A Dnvidia,tegra210-nvenc.yaml4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
11 and newer chips. It is located on the Host1x bus and typically
12 programmed through Host1x channels.
61 nvidia,host1x-class:
63 Host1x class of the engine, used to specify the targeted engine
64 when programming the engine through Host1x channels or when
65 configuring engine-specific behavior in Host1x.
/linux/include/trace/events/
H A Dhost1x.h3 * include/trace/events/host1x.h
5 * host1x event logging to ftrace.
11 #define TRACE_SYSTEM host1x
21 DECLARE_EVENT_CLASS(host1x,
29 DEFINE_EVENT(host1x, host1x_channel_open,
34 DEFINE_EVENT(host1x, host1x_channel_release,
39 DEFINE_EVENT(host1x, host1x_cdma_begin,
44 DEFINE_EVENT(host1x, host1x_cdma_end,

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