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/linux-6.8/arch/parisc/kernel/
Dsignal32.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Signal support for 32-bit kernel builds
4 * Copyright (C) 2001 Matthew Wilcox <willy at parisc-linux.org>
5 * Copyright (C) 2006 Kyle McMartin <kyle at parisc-linux.org>
44 /* When loading 32-bit values into 64-bit registers make in restore_sigcontext32()
45 sure to clear the upper 32-bits */ in restore_sigcontext32()
50 err |= __get_user(compat_reg,&sc->sc_gr[regn]); in restore_sigcontext32()
51 regs->gr[regn] = compat_reg; in restore_sigcontext32()
52 /* Load upper half */ in restore_sigcontext32()
53 err |= __get_user(compat_regt,&rf->rf_gr[regn]); in restore_sigcontext32()
[all …]
Dsignal32.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2001 Matthew Wilcox <willy at parisc-linux.org>
4 * Copyright (C) 2003 Carlos O'Donell <carlos at parisc-linux.org>
11 /* 32-bit ucontext as seen from an 64-bit kernel */
16 /* FIXME: Pad out to get uc_mcontext to start at an 8-byte aligned boundary */
24 /* In a deft move of uber-hackery, we decide to carry the top half of all
25 * 64-bit registers in a non-portable, non-ABI, hidden structure.
31 /* Upper half of all the 64-bit registers that were truncated
32 on a copy to a 32-bit userspace */
48 * The 32-bit ABI wants at least 48 bytes for a function call frame:
[all …]
/linux-6.8/drivers/media/usb/stk1160/
Dstk1160-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * <elezegarcia--a.t--gmail.com>
10 * <rmthomas--a.t--sciolus.org>
19 /* Power-on Strapping Data */
24 #define STK1160_POSV_L_ACDOUT BIT(3)
25 #define STK1160_POSV_L_ACSYNC BIT(2)
30 * with bit #7 (0x?? OR 0x80 to activate).
39 * Bit 0 - Horizontal Decimation Control
42 * Bit 1 - Decimates Half or More Column
43 * 0 Decimates less than half from original column,
[all …]
/linux-6.8/include/uapi/linux/dvb/
Dosd.h1 /* SPDX-License-Identifier: LGPL-2.1+ WITH Linux-syscall-note */
3 * osd.h - DEPRECATED On Screen Display API
18 /* All functions return -2 on "not open" */
26 * Opens OSD with this size and bit depth
27 * returns 0 on success, -1 on DRAM allocation error, -2 on "already open"
57 * returns 0 on success, -1 on error
64 * R,G,B, and a opacity value: 0->transparent, 1..254->mix, 255->pixel
74 * returns 0 on success, -1 on error
77 /* returns color number of pixel <x>,<y>, or -1 */
81 * returns 0 on success, -1 on clipping all pixel (no pixel drawn)
[all …]
/linux-6.8/drivers/soc/ixp4xx/
Dixp4xx-qmgr.c1 // SPDX-License-Identifier: GPL-2.0-only
21 static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
37 __raw_writel(val, &qmgr_regs->acc[queue][0]); in qmgr_put_entry()
43 val = __raw_readl(&qmgr_regs->acc[queue][0]); in qmgr_get_entry()
55 return (__raw_readl(&qmgr_regs->stat1[queue >> 3]) in __qmgr_get_stat1()
62 return (__raw_readl(&qmgr_regs->stat2[queue >> 4]) in __qmgr_get_stat2()
67 * qmgr_stat_empty() - checks if a hardware queue is empty
70 * Returns non-zero value if the queue is empty.
79 * qmgr_stat_below_low_watermark() - checks if a queue is below low watermark
82 * Returns non-zero value if the queue is below low watermark.
[all …]
/linux-6.8/arch/x86/math-emu/
Dreg_round.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 /*---------------------------------------------------------------------------+
10 | Australia. E-mail billm@suburbia.net |
20 | Return value is the tag of the answer, or-ed with FPU_Exception if |
21 | one was raised, or -1 on internal error. |
26 +---------------------------------------------------------------------------*/
28 /*---------------------------------------------------------------------------+
32 | %eax:%ebx 64 bit significand |
33 | %edx 32 bit extension of the significand |
47 | must be non-zero. |
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/linux-6.8/arch/loongarch/include/asm/
Dchecksum.h1 /* SPDX-License-Identifier: GPL-2.0-only */
18 * turns a 32-bit partial checksum (e.g. from csum_partial) into a
19 * 1's complement 16-bit checksum.
26 * swap the two 16-bit halves of sum in csum_fold()
27 * if there is a carry from adding the two 16-bit halves, in csum_fold()
28 * it will carry from the lower half into the upper half, in csum_fold()
29 * giving us the correct sum in the upper half. in csum_fold()
38 * of 32-bit words and is always >= 5.
48 n -= 4; in ip_fast_csum()
54 } while (--n > 0); in ip_fast_csum()
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/linux-6.8/arch/parisc/include/asm/
Dchecksum.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * and adds in "sum" (32-bit)
11 * returns a 32-bit number suitable for feeding into itself
17 * it's best to have buff aligned on a 32-bit boundary
34 " addib,<= -4, %2, 2f\n" in ip_fast_csum()
51 " subi -1, %0, %0\n" in ip_fast_csum()
66 /* add the swapped two 16-bit halves of sum, in csum_fold()
67 a possible carry from adding the two 16-bit halves, in csum_fold()
68 will carry from the lower half into the upper half, in csum_fold()
69 giving us the correct sum in the upper half. */ in csum_fold()
[all …]
/linux-6.8/include/linux/
Dcnt32_to_63.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Extend a 32-bit counter to 63 bits
31 * cnt32_to_63 - Expand a 32-bit counter to a 63-bit counter
35 * a relatively short period making wrap-arounds rather frequent. This
36 * is a problem when implementing sched_clock() for example, where a 64-bit
37 * non-wrapping monotonic value is expected to be returned.
39 * To overcome that limitation, let's extend a 32-bit counter to 63 bits
41 * by the hardware while bits 32 to 62 are stored in memory. The top bit in
42 * memory is used to synchronize with the hardware clock half-period. When
43 * the top bit of both counters (hardware and in memory) differ then the
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/linux-6.8/include/uapi/linux/
Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
63 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
64 #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
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/linux-6.8/drivers/net/ethernet/atheros/atlx/
Datlx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* atlx_hw.h -- common hardware definitions for Attansic network drivers
4 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
5 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
6 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
10 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
149 /* IRQ Anti-Lost Timer Initial Value Register */
228 /* MAC Half-Duplex Control Register */
246 /* Wake-On-Lan control register */
303 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
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/linux-6.8/drivers/clk/sunxi/
Dclk-sun4i-tcon-ch1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk-provider.h>
17 #define TCON_CH1_SCLK2_GATE_BIT BIT(31)
23 #define TCON_CH1_SCLK1_GATE_BIT BIT(15)
24 #define TCON_CH1_SCLK1_HALF_BIT BIT(11)
40 spin_lock_irqsave(&tclk->lock, flags); in tcon_ch1_disable()
41 reg = readl(tclk->reg); in tcon_ch1_disable()
43 writel(reg, tclk->reg); in tcon_ch1_disable()
44 spin_unlock_irqrestore(&tclk->lock, flags); in tcon_ch1_disable()
[all …]
/linux-6.8/drivers/soc/fsl/qe/
Dtsa.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <dt-bindings/soc/cpm1-fsl,tsa.h>
135 return container_of(tsa_serial, struct tsa, serials[tsa_serial->id]); in tsa_serial_get_tsa()
170 switch (tsa_serial->id) { in tsa_serial_connect()
184 dev_err(tsa->dev, "Unsupported serial id %u\n", tsa_serial->id); in tsa_serial_connect()
185 return -EINVAL; in tsa_serial_connect()
188 spin_lock_irqsave(&tsa->lock, flags); in tsa_serial_connect()
189 tsa_clrsetbits32(tsa->si_regs + TSA_SICR, clear, set); in tsa_serial_connect()
190 spin_unlock_irqrestore(&tsa->lock, flags); in tsa_serial_connect()
202 switch (tsa_serial->id) { in tsa_serial_disconnect()
[all …]
/linux-6.8/Documentation/driver-api/iio/
Dtriggered-buffers.rst26 pf->timestamp = iio_get_time_ns((struct indio_dev *)p);
36 for_each_set_bit(bit, active_scan_mask, masklength)
37 buf[i++] = sensor_get_data(bit)
56 * **sensor_iio_pollfunc**, the function that will be used as top half of poll
61 * **sensor_trigger_handler**, the function that will be used as bottom half of
65 top half.
69 .. kernel-doc:: drivers/iio/buffer/industrialio-triggered-buffer.c
/linux-6.8/Documentation/filesystems/
Dqnx6.rst1 .. SPDX-License-Identifier: GPL-2.0
29 ------
35 Blockpointers are 32bit, so the maximum space that can be addressed is
39 ---------------
42 Each qnx6fs got two superblocks, each one having a 64bit serial number.
65 Unused block pointers are always set to ~0 - regardless of root node,
79 0x1000 is the size reserved for each superblock - regardless of the
83 ------
100 The filesize is stored 64bit. Inode counting starts with 1. (while long
104 -----------
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/linux-6.8/include/soc/mscc/
Docelot_vcap.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT)
17 #define OCELOT_VCAP_IS2_MRP_REDIRECT(ocelot, port) ((ocelot)->num_phys_ports + (port))
18 #define OCELOT_VCAP_IS2_MRP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2)
19 #define OCELOT_VCAP_IS2_L2_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 1)
20 #define OCELOT_VCAP_IS2_IPV4_GEN_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 2)
21 #define OCELOT_VCAP_IS2_IPV4_EV_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 3)
22 #define OCELOT_VCAP_IS2_IPV6_GEN_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 4)
23 #define OCELOT_VCAP_IS2_IPV6_EV_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 5)
40 u16 tg_width; /* Type-group width (in bits) */
62 /* VCAP Type-Group values */
[all …]
/linux-6.8/arch/arm64/kvm/hyp/nvhe/
Dmm.c1 // SPDX-License-Identifier: GPL-2.0-only
54 return -EINVAL; in __pkvm_alloc_private_va_range()
61 return -ENOMEM; in __pkvm_alloc_private_va_range()
69 * pkvm_alloc_private_va_range - Allocates a private VA range.
169 size = end - start; in hyp_back_vmemmap()
201 return -EINVAL; in pkvm_cpu_set_vector()
235 kvm_pte_t pte, *ptep = slot->ptep; in hyp_fixmap_map()
243 return (void *)slot->addr; in hyp_fixmap_map()
248 kvm_pte_t *ptep = slot->ptep; in fixmap_clear_slot()
249 u64 addr = slot->addr; in fixmap_clear_slot()
[all …]
/linux-6.8/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_fwif.h1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2014-2019 Intel Corporation
54 * Work queue is circular buffer used to submit complex (multi-lrc) submissions
73 #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0)
74 #define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1)
75 #define GUC_STAGE_DESC_ATTR_KERNEL BIT(2)
76 #define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3)
77 #define GUC_STAGE_DESC_ATTR_RESET BIT(4)
78 #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5)
79 #define GUC_STAGE_DESC_ATTR_PCH BIT(6)
[all …]
/linux-6.8/drivers/soc/aspeed/
Daspeed-lpc-ctrl.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <linux/aspeed-lpc-ctrl.h>
19 #define DEVICE_NAME "aspeed-lpc-ctrl"
22 #define HICR5_ENL2H BIT(8)
23 #define HICR5_ENFWH BIT(10)
26 #define SW_FWH2AHB BIT(17)
45 return container_of(file->private_data, struct aspeed_lpc_ctrl, in file_aspeed_lpc_ctrl()
52 unsigned long vsize = vma->vm_end - vma->vm_start; in aspeed_lpc_ctrl_mmap()
53 pgprot_t prot = vma->vm_page_prot; in aspeed_lpc_ctrl_mmap()
55 if (vma->vm_pgoff + vma_pages(vma) > lpc_ctrl->mem_size >> PAGE_SHIFT) in aspeed_lpc_ctrl_mmap()
[all …]
/linux-6.8/Documentation/devicetree/bindings/dma/
Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a five-cell specifier for each channel:
21 3. A 32bit mask specifying the DMA channel configuration
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
30 -bit 8-9: Source increment offset size
[all …]
/linux-6.8/tools/testing/selftests/powerpc/tm/
Dtm-signal-context-chk-vsx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
34 #define VSX20 20 /* First VSX register to check in vsr20-vsr31 subset */
43 /* First context will be set with these values, i.e. non-speculative */
51 {-1, -2, -3, -4 },{-5, -6, -7, -8 },{-9, -10,-11,-12},
52 {-13,-14,-15,-16},{-17,-18,-19,-20},{-21,-22,-23,-24},
53 {-25,-26,-27,-28},{-29,-30,-31,-32},{-33,-34,-35,-36},
54 {-37,-38,-39,-40},{-41,-42,-43,-44},{-45,-46,-47,-48}
63 ucontext_t *tm_ucp = ucp->uc_link; in signal_usr1()
68 * FP registers (f0-31) overlap the most significant 64 bits of VSX in signal_usr1()
69 * registers vsr0-31, whilst VMX registers vr0-31, being 128-bit like in signal_usr1()
[all …]
/linux-6.8/drivers/net/ethernet/intel/igc/
Digc_phy.c1 // SPDX-License-Identifier: GPL-2.0
8 * igc_check_reset_block - Check if PHY reset is blocked
26 * igc_get_phy_id - Retrieve the PHY ID and revision
34 struct igc_phy_info *phy = &hw->phy; in igc_get_phy_id()
38 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in igc_get_phy_id()
42 phy->id = (u32)(phy_id << 16); in igc_get_phy_id()
44 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); in igc_get_phy_id()
48 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); in igc_get_phy_id()
49 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); in igc_get_phy_id()
56 * igc_phy_has_link - Polls PHY for link
[all …]
/linux-6.8/drivers/mtd/spi-nor/
Dsfdp.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/mtd/spi-nor.h>
14 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
16 (((p)->parameter_table_pointer[2] << 16) | \
17 ((p)->parameter_table_pointer[1] << 8) | \
18 ((p)->parameter_table_pointer[0] << 0))
19 #define SFDP_PARAM_HEADER_PARAM_LEN(p) ((p)->length * 4)
23 #define SFDP_4BAIT_ID 0xff84 /* 4-byte Address Instruction Table */
31 * Register Map Offsets for Multi-Chip
41 u8 nph; /* 0-base number of parameter headers */
[all …]
/linux-6.8/drivers/net/ethernet/aquantia/atlantic/macsec/
Dmacsec_struct.h1 /* SPDX-License-Identifier: GPL-2.0-only */
13 /*! This is used to store the 48 bit value used to compare SA, DA or
14 * halfDA+half SA value.
17 /*! This is used to store the 16 bit ethertype value used for
21 /*! The match mask is per-nibble. 0 means don't care, i.e. every value
22 * will match successfully. The total data is 64 bit, i.e. 16 nibbles
29 * 3: compare half DA + half SA
52 /*! The 8 bit value used to compare with extracted value for byte 3. */
54 /*! The 8 bit value used to compare with extracted value for byte 2. */
56 /*! The 8 bit value used to compare with extracted value for byte 1. */
[all …]
/linux-6.8/arch/sparc/include/asm/
Dbbc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
40 #define BBC_I2C_1_S1 0x30 /* [B] I2C ctrlr-1 reg S1 */
41 #define BBC_I2C_1_S0 0x31 /* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/
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