Searched full:gpll0 (Results 1 – 25 of 86) sorted by relevance
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| /src/sys/contrib/device-tree/Bindings/clock/ |
| H A D | qcom,mmcc.yaml | 97 - description: MMSS GPLL0 voted clock
98 - description: GPLL0 voted clock
125 - description: MMSS GPLL0 voted clock
126 - description: GPLL0 voted clock
164 - description: MMSS GPLL0 voted clock
165 - description: GPLL0 clock
166 - description: GPLL0 voted clock
181 - const: gpll0
228 - const: gpll0
258 - const: gpll0
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| H A D | qcom,msm8998-gpucc.yaml | 25 - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
30 - const: gpll0
54 clock-names = "xo", "gpll0";
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| H A D | qcom,qcs615-gpucc.yaml | 25 - description: GPLL0 main branch source
26 - description: GPLL0 GPUCC div branch source
42 <&gcc GPLL0>,
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| H A D | qcom,sm6115-gpucc.yaml | 26 - description: GPLL0 main branch source
27 - description: GPLL0 main div source
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| H A D | qcom,sdm845-gpucc.yaml | 25 - description: GPLL0 main branch source
26 - description: GPLL0 div branch source
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| H A D | qcom,gpucc-sm8350.yaml | 26 - description: GPLL0 main branch source
27 - description: GPLL0 div branch source
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| H A D | qcom,sc7180-gpucc.yaml | 25 - description: GPLL0 main branch source
26 - description: GPLL0 div branch source
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| H A D | qcom,gpucc-sdm660.yaml | 27 - description: GPLL0 main gpu branch
28 - description: GPLL0 divider gpu branch
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| H A D | qcom,qcm2290-dispcc.yaml | 26 - description: GPLL0 source from GCC
27 - description: GPLL0 div source from GCC
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| H A D | qcom,qcm2290-gpucc.yaml | 30 - description: GPLL0 main branch source
31 - description: GPLL0 div branch source
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| H A D | qcom,sm6375-gpucc.yaml | 26 - description: GPLL0 main branch source
27 - description: GPLL0 div branch source
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| H A D | qcom,sm8450-gpucc.yaml | 42 - description: GPLL0 main branch source
43 - description: GPLL0 div branch source
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| H A D | qcom,sdm845-dispcc.yaml | 28 - description: GPLL0 source from GCC
29 - description: GPLL0 div source from GCC
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| H A D | qcom,gpucc.yaml | 47 - description: GPLL0 main branch source
48 - description: GPLL0 div branch source
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| H A D | qcom,sm6375-dispcc.yaml | 28 - description: GPLL0 source from GCC
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| H A D | qcom,sm6125-gpucc.yaml | 26 - description: GPLL0 main branch source
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| H A D | qcom,sm6115-dispcc.yaml | 29 - description: GPLL0 DISP DIV clock from GCC
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| H A D | qcom,qcs615-dispcc.yaml | 25 - description: GPLL0 clock source from GCC
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| H A D | qcom,milos-dispcc.yaml | 27 - description: GPLL0 source from GCC
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| H A D | qcom,qdu1000-ecpricc.yaml | 30 - description: GPLL0 source from GCC
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| H A D | qcom,dispcc-sm6350.yaml | 25 - description: GPLL0 source from GCC
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| /src/sys/contrib/device-tree/Bindings/interconnect/ |
| H A D | qcom,osm-l3.yaml | 73 #define GPLL0 165
80 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
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| /src/sys/contrib/device-tree/Bindings/remoteproc/ |
| H A D | qcom,msm8996-mss-pil.yaml | 220 - description: GCC MSS GPLL0 clock
255 - description: GCC MSS GPLL0 clock
292 - description: GCC MSS GPLL0 clock
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| /src/sys/contrib/device-tree/Bindings/cpufreq/ |
| H A D | cpufreq-qcom-hw.txt | 16 Definition: clock handle for XO clock and GPLL0 clock.
167 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
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| /src/sys/contrib/device-tree/Bindings/mailbox/ |
| H A D | qcom,apcs-kpss-global.yaml | 173 - description: GCC GPLL0 clock source
178 - const: gpll0
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