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/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dti,c64x+megamod-pic.txt2 -------------------
8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
12 --------------------
13 - compatible: Should be "ti,c64x+core-pic";
14 - #interrupt-cells: <1>
17 ------------------------------
18 Single cell specifying the core interrupt priority level (4-15) where
22 -------
23 core_pic: interrupt-controller@0 {
24 interrupt-controller;
[all …]
Dimg,pdc-intc.txt10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
/linux-5.10/Documentation/devicetree/bindings/power/supply/
Dsbs,sbs-manager.txt1 Binding for sbs-manager
4 - compatible: "<vendor>,<part-number>", "sbs,sbs-charger" as fallback. The part
7 - reg: integer, i2c address of the device. Should be <0xa>.
9 - gpio-controller: Marks the port as GPIO controller.
10 See "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt.
11 - #gpio-cells: Should be <2>. The first cell is the pin number, the second cell
13 See "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt.
15 From OS view the device is basically an i2c-mux used to communicate with up to
16 four smart battery devices at address 0xb. The driver actually implements this
17 behaviour. So standard i2c-mux nodes can be used to register up to four slave
[all …]
/linux-5.10/Documentation/devicetree/bindings/net/
Dcavium-mix.txt4 - compatible: "cavium,octeon-5750-mix"
9 - reg: The base addresses of four separate register banks. The first
15 - cell-index: A single cell specifying which portion of the shared
18 - interrupts: Two interrupt specifiers. The first is the MIX
21 - phy-handle: Optional, see ethernet.txt file in the same directory.
25 compatible = "cavium,octeon-5750-mix";
30 cell-index = <1>;
32 local-mac-address = [ 00 0f b7 10 63 54 ];
33 phy-handle = <&phy1>;
/linux-5.10/arch/powerpc/include/asm/
Dcell-pmu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Cell Broadband Engine Performance Monitor
15 /* The Cell PMU has four hardware performance counters, which can be
16 * configured as four 32-bit counters or eight 16-bit counters.
22 #define CBE_PM_16BIT_CTR(ctr) (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
52 #define CBE_PM_CTR_OVERFLOW_INTR(ctr) (1 << (31 - ((ctr) & 7)))
/linux-5.10/Documentation/devicetree/bindings/gpio/
Dcavium-octeon-gpio.txt4 - compatible: "cavium,octeon-3860-gpio"
8 - reg: The base address of the GPIO unit's register bank.
10 - gpio-controller: This is a GPIO controller.
12 - #gpio-cells: Must be <2>. The first cell is the GPIO pin.
14 - interrupt-controller: The GPIO controller is also an interrupt
18 - #interrupt-cells: Must be <2>. The first cell is the GPIO pin
19 connected to the interrupt source. The second cell is the interrupt
20 triggering protocol and may have one of four values:
21 1 - edge triggered on the rising edge.
22 2 - edge triggered on the falling edge
[all …]
/linux-5.10/Documentation/devicetree/bindings/sound/
Dcirrus,madera.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
21 include/dt-bindings/sound/madera.h
26 '#sound-dai-cells':
28 The first cell indicating the audio interface.
34 of 24 cells, with four cells per input in the order INnAL,
35 INnAR INnBL INnBR. For non-muxed inputs the first two cells
43 $ref: /schemas/types.yaml#/definitions/uint32-array
[all …]
/linux-5.10/Documentation/devicetree/bindings/mfd/
Dti,lp87561-q1.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/ti,lp87561-q1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI LP87561-Q1 single 4-phase output buck converter
10 - Keerthy <j-keerthy@ti.com>
14 const: ti,lp87561-q1
20 gpio-controller: true
22 '#gpio-cells':
24 The first cell is the pin number.
[all …]
Dti,lp87524-q1.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/ti,lp87524-q1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI LP87524-Q1 four 1-phase output buck converter
10 - Keerthy <j-keerthy@ti.com>
14 const: ti,lp87524-q1
20 gpio-controller: true
22 '#gpio-cells':
24 The first cell is the pin number.
[all …]
/linux-5.10/Documentation/userspace-api/media/v4l/
Dpixfmt-yuv410.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-YVU410:
4 .. _v4l2-pix-fmt-yuv410:
20 components are separated into three sub-images or planes. The Y plane is
24 belongs to 16 pixels, a four-by-four square of the image. Following the
30 have ¼ as many pad bytes after their rows. In other words, four Cx rows
35 Each cell is one byte.
40 .. flat-table::
41 :header-rows: 0
42 :stub-columns: 0
[all …]
Dpixfmt-vyuy.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-VYUY:
17 In this format each four bytes is two pixels. Each four bytes is two
23 Each cell is one byte.
26 .. flat-table::
27 :header-rows: 0
28 :stub-columns: 0
30 * - start + 0:
31 - Cr\ :sub:`00`
32 - Y'\ :sub:`00`
[all …]
Dpixfmt-yvyu.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-YVYU:
17 In this format each four bytes is two pixels. Each four bytes is two
23 Each cell is one byte.
26 .. flat-table::
27 :header-rows: 0
28 :stub-columns: 0
30 * - start + 0:
31 - Y'\ :sub:`00`
32 - Cr\ :sub:`00`
[all …]
Dpixfmt-uyvy.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-UYVY:
17 In this format each four bytes is two pixels. Each four bytes is two
23 Each cell is one byte.
26 .. flat-table::
27 :header-rows: 0
28 :stub-columns: 0
30 * - start + 0:
31 - Cb\ :sub:`00`
32 - Y'\ :sub:`00`
[all …]
Dpixfmt-yuyv.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-YUYV:
17 In this format each four bytes is two pixels. Each four bytes is two
24 Each cell is one byte.
29 .. flat-table::
30 :header-rows: 0
31 :stub-columns: 0
33 * - start + 0:
34 - Y'\ :sub:`00`
35 - Cb\ :sub:`00`
[all …]
Dpixfmt-y41p.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-Y41P:
18 four Y's, and the second CbCr pair goes with the other four Y's. The Cb
23 :ref:`V4L2_PIX_FMT_YUV411P <V4L2-PIX-FMT-YUV411P>`. Y41P is derived
28 Each cell is one byte.
33 .. flat-table::
34 :header-rows: 0
35 :stub-columns: 0
37 * - start + 0:
38 - Cb\ :sub:`00`
[all …]
Dpixfmt-srggb10p.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB10P:
4 .. _v4l2-pix-fmt-sbggr10p:
5 .. _v4l2-pix-fmt-sgbrg10p:
6 .. _v4l2-pix-fmt-sgrbg10p:
16 10-bit packed Bayer formats
22 These four pixel formats are packed raw sRGB / Bayer formats with 10
23 bits per sample. Every four consecutive samples are packed into 5
28 Each n-pixel row contains n/2 green samples and n/2 blue or red samples,
29 with alternating green-red and green-blue rows. They are conventionally
[all …]
Dpixfmt-srggb14p.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB14P:
4 .. _v4l2-pix-fmt-sbggr14p:
5 .. _v4l2-pix-fmt-sgbrg14p:
6 .. _v4l2-pix-fmt-sgrbg14p:
17 14-bit packed Bayer formats
23 These four pixel formats are packed raw sRGB / Bayer formats with 14
24 bits per colour. Every four consecutive samples are packed into seven
25 bytes. Each of the first four bytes contain the eight high order bits
29 Each n-pixel row contains n/2 green samples and n/2 blue or red samples,
[all …]
Dpixfmt-srggb12p.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB12P:
4 .. _v4l2-pix-fmt-sbggr12p:
5 .. _v4l2-pix-fmt-sgbrg12p:
6 .. _v4l2-pix-fmt-sgrbg12p:
13 12-bit packed Bayer formats
14 ---------------------------
20 These four pixel formats are packed raw sRGB / Bayer formats with 12
23 the pixels, and the third byte contains the four least significants
26 Each n-pixel row contains n/2 green samples and n/2 blue or red
[all …]
Dpixfmt-m420.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-M420:
10 YUV 4:2:0. Hybrid plane line-interleaved layout.
22 directions. Each CbCr pair belongs to four pixels. For example,
30 Each cell is one byte.
33 .. flat-table::
34 :header-rows: 0
35 :stub-columns: 0
37 * - start + 0:
38 - Y'\ :sub:`00`
[all …]
/linux-5.10/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dgpio.txt1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
14 second cell is used to specify optional parameters (currently unused).
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
[all …]
/linux-5.10/Documentation/devicetree/bindings/clock/
Dpistachio-clock.txt4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
18 ----------------------
21 co-processor), audio, and several peripherals.
24 - compatible: Must be "img,pistachio-clk".
[all …]
/linux-5.10/Documentation/devicetree/bindings/dma/
Dst,stm32-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
25 -bit 15: Peripheral Increment Offset Size
[all …]
/linux-5.10/Documentation/filesystems/spufs/
Dspufs.rst1 .. SPDX-License-Identifier: GPL-2.0
10 spufs - the SPU file system
16 The SPU file system is used on PowerPC machines that implement the Cell
26 logical SPU. Users can change permissions on those files, but not actu-
43 The files in spufs mostly follow the standard behavior for regular sys-
55 All files support the chmod(2)/fchmod(2) and chown(2)/fchown(2) opera-
81 The first SPU to CPU communication mailbox. This file is read-only and
82 can be read in units of 32 bits. The file can only be used in non-
87 If a count smaller than four is requested, read returns -1 and
89 box, the return value is set to -1 and errno becomes EAGAIN.
[all …]
/linux-5.10/drivers/bus/
Dhisi_lpc.c1 // SPDX-License-Identifier: GPL-2.0+
22 #define DRV_NAME "hisi-lpc"
42 /* The max IO cycle counts supported is four per operation at maximum */
84 return (status & LPC_REG_OP_STATUS_FINISHED) ? 0 : -EIO; in wait_lpc_idle()
86 } while (--waitcnt); in wait_lpc_idle()
88 return -ETIME; in wait_lpc_idle()
92 * hisi_lpc_target_in - trigger a series of LPC cycles for read operation
99 * Returns 0 on success, non-zero on fail.
110 if (!buf || !opcnt || !para || !para->csize || !lpcdev) in hisi_lpc_target_in()
111 return -EINVAL; in hisi_lpc_target_in()
[all …]
/linux-5.10/Documentation/devicetree/bindings/mailbox/
Dallwinner,sun6i-a31-msgbox.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mailbox/allwinner,sun6i-a31-msgbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Samuel Holland <samuel@sholland.org>
14 two-user mailbox controller containing 8 unidirectional FIFOs. An interrupt
17 hold four 32-bit messages; when a FIFO is full, clients must wait before
20 Refer to ./mailbox.txt for generic information about mailbox device-tree
26 - items:
27 - enum:
[all …]

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