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/qemu/qapi/
H A Daudio.json1 # -*- mode: python -*-
4 # Copyright (C) 2015-2019 Zoltán Kővágó <DirtY.iCE.hu@gmail.com>
7 # See the COPYING file in the top-level directory.
19 # @mixing-engine: use QEMU's mixing engine to mix all streams inside
21 # backend. When set to off, fixed-settings must be also off
24 # @fixed-settings: use fixed settings for host input/output. When
25 # off, frequency, channels and format must not be specified
28 # @frequency: frequency to use when using fixed settings (default
31 # @channels: number of channels when using fixed settings (default 2)
35 # @format: sample format to use when using fixed settings (default
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/qemu/hw/arm/
H A Dnetduinoplus2.c28 #include "hw/qdev-properties.h"
29 #include "hw/qdev-clock.h"
30 #include "qemu/error-report.h"
34 /* Main SYSCLK frequency in Hz (168MHz) */
42 /* This clock doesn't need migration because it is fixed-frequency */ in netduinoplus2_init()
51 armv7m_load_kernel(STM32F405_SOC(dev)->armv7m.cpu, in netduinoplus2_init()
52 machine->kernel_filename, in netduinoplus2_init()
59 ARM_CPU_TYPE_NAME("cortex-m4"), in netduinoplus2_machine_init()
63 mc->desc = "Netduino Plus 2 Machine (Cortex-M4)"; in netduinoplus2_machine_init()
64 mc->init = netduinoplus2_init; in netduinoplus2_machine_init()
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H A Dnetduino2.c28 #include "hw/qdev-properties.h"
29 #include "hw/qdev-clock.h"
30 #include "qemu/error-report.h"
34 /* Main SYSCLK frequency in Hz (120MHz) */
42 /* This clock doesn't need migration because it is fixed-frequency */ in netduino2_init()
51 armv7m_load_kernel(STM32F205_SOC(dev)->armv7m.cpu, machine->kernel_filename, in netduino2_init()
58 ARM_CPU_TYPE_NAME("cortex-m3"), in netduino2_machine_init()
62 mc->desc = "Netduino 2 Machine (Cortex-M3)"; in netduino2_machine_init()
63 mc->init = netduino2_init; in netduino2_machine_init()
64 mc->valid_cpu_types = valid_cpu_types; in netduino2_machine_init()
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H A Dstm32vldiscovery.c29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-clock.h"
31 #include "qemu/error-report.h"
37 /* Main SYSCLK frequency in Hz (24MHz) */
45 /* This clock doesn't need migration because it is fixed-frequency */ in stm32vldiscovery_init()
54 armv7m_load_kernel(STM32F100_SOC(dev)->armv7m.cpu, in stm32vldiscovery_init()
55 machine->kernel_filename, in stm32vldiscovery_init()
62 ARM_CPU_TYPE_NAME("cortex-m3"), in stm32vldiscovery_machine_init()
66 mc->desc = "ST STM32VLDISCOVERY (Cortex-M3)"; in stm32vldiscovery_machine_init()
67 mc->init = stm32vldiscovery_init; in stm32vldiscovery_machine_init()
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H A Dolimex-stm32-h405.c3 * Olimex STM32-H405 machine
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-clock.h"
31 #include "qemu/error-report.h"
35 /* olimex-stm32-h405 implementation is derived from netduinoplus2 */
37 /* Main SYSCLK frequency in Hz (168MHz) */
45 /* This clock doesn't need migration because it is fixed-frequency */ in olimex_stm32_h405_init()
54 armv7m_load_kernel(STM32F405_SOC(dev)->armv7m.cpu, in olimex_stm32_h405_init()
55 machine->kernel_filename, in olimex_stm32_h405_init()
62 ARM_CPU_TYPE_NAME("cortex-m4"), in olimex_stm32_h405_machine_init()
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H A Dcubieboard.c20 #include "qemu/error-report.h"
22 #include "hw/qdev-properties.h"
23 #include "hw/arm/allwinner-a10.h"
43 if (machine->firmware) { in cubieboard_init()
48 /* This board has fixed size RAM (512MiB or 1GiB) */ in cubieboard_init()
49 if (machine->ram_size != 512 * MiB && in cubieboard_init()
50 machine->ram_size != 1 * GiB) { in cubieboard_init()
59 if (!object_property_set_int(OBJECT(&a10->emac), "phy-addr", 1, &err)) { in cubieboard_init()
64 if (!object_property_set_int(OBJECT(&a10->timer), "clk0-freq", 32768, in cubieboard_init()
66 error_reportf_err(err, "Couldn't set clk0 frequency: "); in cubieboard_init()
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H A Dmsf2-som.c4 * M2S-FG484 SOM hardware architecture specification:
5 * https://www.emcraft.com/jdownloads/som/m2s/m2s-som-ha.pdf
31 #include "qemu/error-report.h"
33 #include "hw/qdev-properties.h"
35 #include "hw/qdev-clock.h"
36 #include "system/address-spaces.h"
37 #include "hw/arm/msf2-soc.h"
57 memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE, in emcraft_sf2_s2s010_init()
63 qdev_prop_set_string(dev, "part-name", "M2S010"); in emcraft_sf2_s2s010_init()
64 qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE); in emcraft_sf2_s2s010_init()
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H A Dnrf51_soc.c8 * the COPYING file in the top-level directory.
15 #include "hw/qdev-clock.h"
24 * are supported in the future, add a sub-class of NRF51SoC for
47 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", in clock_write()
64 if (!s->board_memory) { in nrf51_soc_realize()
70 * HCLK on this SoC is fixed, so we set up sysclk ourselves and in nrf51_soc_realize()
73 if (clock_has_source(s->sysclk)) { in nrf51_soc_realize()
77 /* This clock doesn't need migration because it is fixed-frequency */ in nrf51_soc_realize()
78 clock_set_hz(s->sysclk, HCLK_FRQ); in nrf51_soc_realize()
79 qdev_connect_clock_in(DEVICE(&s->armv7m), "cpuclk", s->sysclk); in nrf51_soc_realize()
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H A Dmsf2-soc.c4 * Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>
28 #include "system/address-spaces.h"
29 #include "hw/char/serial-mm.h"
30 #include "hw/arm/msf2-soc.h"
32 #include "hw/qdev-clock.h"
66 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); in m2sxxx_soc_initfn()
68 object_initialize_child(obj, "sysreg", &s->sysreg, TYPE_MSF2_SYSREG); in m2sxxx_soc_initfn()
70 object_initialize_child(obj, "timer", &s->timer, TYPE_MSS_TIMER); in m2sxxx_soc_initfn()
73 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_MSS_SPI); in m2sxxx_soc_initfn()
76 object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC); in m2sxxx_soc_initfn()
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H A Dintegratorcp.c4 * Copyright (c) 2005-2007 CodeSourcery.
19 #include "system/address-spaces.h"
23 #include "qemu/error-report.h"
30 #include "target/arm/cpu-qom.h"
98 return s->cm_osc; in integratorcm_read()
100 return s->cm_ctrl; in integratorcm_read()
104 if (s->cm_lock == 0xa05f) { in integratorcm_read()
107 return s->cm_lock; in integratorcm_read()
110 /* ??? High frequency timer. */ in integratorcm_read()
113 return s->cm_auxosc; in integratorcm_read()
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H A Dmps2.c17 * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
18 * "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386
19 * "mps2-an500" -- Cortex-M7 as documented in ARM Application Note AN500
20 * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
24 * https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system
31 #include "qemu/error-report.h"
34 #include "hw/or-irq.h"
36 #include "system/address-spaces.h"
38 #include "hw/qdev-properties.h"
40 #include "hw/char/cmsdk-apb-uart.h"
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/qemu/tests/functional/acpi-bits/bits-tests/
H A Dtestacpi.py24 # SPDX-License-Identifier: BSD-3-Clause
46 testsuite.add_test("ACPI FACP (Fixed ACPI Description Table)", test_facp, submenu="ACPI Tests")
93 # We special-case None here to avoid a double-failure for CPUs without a _PSS
114 …testsuite.test("_PSS must list Pstates in descending order of frequency", frequencies == sorted(fr…
122 """Execute and verify frequency for each Pstate in the _PSS"""
162 # Detecting Turbo frequency requires at least 2 pstates
163 # since turbo frequency = max non-turbo frequency + 1
170 while (time.time() - start < 2):
175 # Abort the test if no cpu frequency is not available
189 …testsuite.test("P{}: Turbo measured frequency {} >= expected {} MHz".format(n, aperf, pstate.core_…
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/qemu/hw/core/
H A Dptimer.c12 #include "qemu/host-utils.h"
13 #include "exec/replay-core.h"
20 #define DELTA_NO_ADJUST -1
45 /* Use a bottom-half routine to avoid reentrancy issues. */
48 s->callback(s->callback_opaque); in ptimer_trigger()
65 (s->policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT)) { in ptimer_reload()
68 if (s->delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER) in ptimer_reload()
78 delta = s->delta; in ptimer_reload()
79 period = s->period; in ptimer_reload()
80 period_frac = s->period_frac; in ptimer_reload()
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H A Dsysbus-fdt.c30 #include "hw/core/sysbus-fdt.h"
31 #include "qemu/error-report.h"
34 #include "hw/platform-bus.h"
35 #include "hw/vfio/vfio-platform.h"
36 #include "hw/vfio/vfio-calxeda-xgmac.h"
37 #include "hw/vfio/vfio-amd-xgbe.h"
38 #include "hw/vfio/vfio-region.h"
40 #include "hw/uefi/var-service-api.h"
103 if (props[i].optional && prop_len == -FDT_ERR_NOTFOUND) { in copy_properties_from_host()
121 {"#clock-cells", false},
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/qemu/hw/misc/
H A Dimx8mp_ccm.c8 * SPDX-License-Identifier: GPL-2.0-or-later
25 memset(s->ccm, 0, sizeof(s->ccm)); in imx8mp_ccm_reset()
91 memory_region_init_io(&s->iomem, in imx8mp_ccm_init()
94 s->ccm, in imx8mp_ccm_init()
96 sizeof(s->ccm)); in imx8mp_ccm_init()
98 sysbus_init_mmio(sd, &s->iomem); in imx8mp_ccm_init()
115 * have fixed frequencies and we can provide requested frequency in imx8mp_ccm_get_clock_frequency()
159 dc->vmsd = &imx8mp_ccm_vmstate; in imx8mp_ccm_class_init()
160 dc->desc = "i.MX 8M Plus Clock Control Module"; in imx8mp_ccm_class_init()
162 ccm->get_clock_frequency = imx8mp_ccm_get_clock_frequency; in imx8mp_ccm_class_init()
H A Dimx7_ccm.c9 * See the COPYING file in the top-level directory.
27 memset(s->pmu, 0, sizeof(s->pmu)); in imx7_analog_reset()
28 memset(s->analog, 0, sizeof(s->analog)); in imx7_analog_reset()
30 s->analog[ANALOG_PLL_ARM] = 0x00002042; in imx7_analog_reset()
31 s->analog[ANALOG_PLL_DDR] = 0x0060302c; in imx7_analog_reset()
32 s->analog[ANALOG_PLL_DDR_SS] = 0x00000000; in imx7_analog_reset()
33 s->analog[ANALOG_PLL_DDR_NUM] = 0x06aaac4d; in imx7_analog_reset()
34 s->analog[ANALOG_PLL_DDR_DENOM] = 0x100003ec; in imx7_analog_reset()
35 s->analog[ANALOG_PLL_480] = 0x00002000; in imx7_analog_reset()
36 s->analog[ANALOG_PLL_480A] = 0x52605a56; in imx7_analog_reset()
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/qemu/hw/rx/
H A Drx62n.c8 * Copyright (c) 2020 Philippe Mathieu-Daudé
25 #include "qemu/error-report.h"
30 #include "hw/qdev-properties.h"
78 * IRQ -> IPR mapping table
79 * 0x00 - 0x91: IPR no (IPR00 to IPR91)
137 object_initialize_child(OBJECT(s), "icu", &s->icu, TYPE_RX_ICU); in register_icu()
138 icu = SYS_BUS_DEVICE(&s->icu); in register_icu()
144 qdev_prop_set_array(DEVICE(icu), "ipr-map", ipr_map); in register_icu()
150 qdev_prop_set_array(DEVICE(icu), "trigger-level", trigger_level); in register_icu()
153 sysbus_connect_irq(icu, 0, qdev_get_gpio_in(DEVICE(&s->cpu), RX_CPU_IRQ)); in register_icu()
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/qemu/docs/devel/
H A Dclocks.rst5 ----------------
28 +---------+ +----------------------+ +--------------+
30 | | | +-------+ +-------+ | | +-------+ |
31 | |>>-+-->>|Clock 2| |Clock 3|>>--->>|Clock 6| |
32 +---------+ | | | (in) | | (out) | | | | (in) | |
33 | | +-------+ +-------+ | | +-------+ |
34 | | +-------+ | +--------------+
36 | | | (out) | | +--------------+
37 | | +-------+ | | Device D |
38 | | +-------+ | | +-------+ |
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/qemu/hw/avr/
H A Datmega.c4 * Copyright (c) 2019-2020 Philippe Mathieu-Daudé
7 * See the COPYING file in the top-level directory.
8 * SPDX-License-Identifier: GPL-2.0-or-later
17 #include "system/address-spaces.h"
19 #include "hw/qdev-properties.h"
196 int cpu_irq = k->irq[peripheral_index]; in connect_peripheral_irq()
203 cpu_irq -= 2; in connect_peripheral_irq()
213 unsigned power_index = k->dev[peripheral_index].power_index; in connect_power_reduction_gpio()
214 assert(k->dev[power_index].addr); in connect_power_reduction_gpio()
215 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwr[power_index - POWER0]), in connect_power_reduction_gpio()
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/qemu/hw/riscv/
H A Dsifive_u.c2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
15 * 5) OTP (One-Time Programmable) memory with stored serial number
39 #include "qemu/error-report.h"
65 /* CLINT timebase frequency */
99 uint64_t mem_size = ms->ram_size; in create_fdt()
111 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt()
114 fdt = ms->fdt = create_device_tree(&s->fdt_size); in create_fdt()
122 "sifive,hifive-unleashed-a00"); in create_fdt()
123 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); in create_fdt()
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/qemu/include/standard-headers/linux/
H A Dvirtio_snd.h1 /* SPDX-License-Identifier: BSD-3-Clause */
8 #include "standard-headers/linux/virtio_types.h"
132 /* 0 ... virtio_snd_config::jacks - 1 */
172 /* 0 ... virtio_snd_config::streams - 1 */
279 /* 0 ... virtio_snd_config::streams - 1 */
297 /* 0 ... virtio_snd_config::chmaps - 1 */
311 VIRTIO_SND_CHMAP_LFE, /* low frequency (LFE) */
362 /* 0 ... virtio_snd_config::controls - 1 */
406 /* index for an element with a non-unique name */
418 /* fixed step size for value (0 = variable size) */
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/qemu/hw/ppc/
H A De500.c2 * QEMU PowerPC e500-based platforms
20 #include "qemu/guest-random.h"
24 #include "e500-ccsr.h"
26 #include "qemu/config-file.h"
28 #include "hw/char/serial-mm.h"
30 #include "system/block-backend-io.h"
40 #include "hw/qdev-properties.h"
44 #include "qemu/host-utils.h"
46 #include "hw/pci-host/ppce500.h"
47 #include "qemu/error-report.h"
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/qemu/pc-bios/
HDu-boot.e500 ... --------------------- ...
/qemu/audio/
H A Dossaudio.c4 * Copyright (c) 2003-2005 Vassili Karpov (malc)
28 #include "qemu/main-loop.h"
30 #include "qemu/host-utils.h"
105 *fdp = -1; in oss_anal_close()
124 qemu_set_fd_handler(oss->fd, NULL, oss_helper_poll_out, hw->s); in oss_poll_out()
131 qemu_set_fd_handler(oss->fd, oss_helper_poll_in, NULL, hw->s); in oss_poll_in()
201 return -1; in oss_to_audfmt()
211 dolog ("format | %10d | %10d\n", req->fmt, obt->fmt); in oss_dump_info()
213 req->nchannels, obt->nchannels); in oss_dump_info()
214 dolog ("frequency | %10d | %10d\n", req->freq, obt->freq); in oss_dump_info()
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/qemu/hw/sh4/
H A Dsh7750_regs.h2 * SH-7750 memory-mapped registers
6 * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
8 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
55 /* Page Table Entry High register - PTEH */
64 /* Page Table Entry Low register - PTEL */
70 #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */
73 #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */
74 #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */
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