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/linux/arch/arm/mach-omap1/
H A Dams-delta-fiq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Amstrad E3 FIQ handling
10 * Parts of this code are taken from linux/arch/arm/mach-omap/irq.c
20 #include <linux/platform_data/ams-delta-fiq.h>
23 #include <asm/fiq.h>
24 #include <linux/soc/ti/omap1-io.h>
27 #include "ams-delta-fiq.h"
28 #include "board-ams-delta.h"
31 .name = "ams-delta-fiq"
35 * This buffer is shared between FIQ and IRQ contexts.
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H A Dboard-ams-delta.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/board-ams-delta.c
5 * Modified from board-generic.c
19 #include <linux/mtd/nand-gpio.h>
30 #include <linux/platform_data/gpio-omap.h>
31 #include <linux/soc/ti/omap1-mux.h>
34 #include <asm/mach-types.h>
38 #include <linux/platform_data/keypad-omap.h>
42 #include "ams-delta-fiq.h"
43 #include "board-ams-delta.h"
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
74 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
87 timer provides more intra-tick resolution than the 32KHz timer,
91 bool "Enable wake-up events for serial ports"
109 device drivers work properly.
149 have such a device.
154 select FIQ
161 if you have such a device.
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dapple,aic2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
18 - Level-triggered hardware IRQs wired to SoC blocks
19 - Single mask bit per IRQ
20 - Automatic masking on event delivery (auto-ack)
21 - Software triggering (ORed with hw line)
22 - Automatic prioritization (single event/ack register per CPU, lower IRQs =
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H A Dapple,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
22 - Automatic masking on event delivery (auto-ack)
23 - Software triggering (ORed with hw line)
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H A Dst,stih407-irq-syscfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/st,stih407-irq-syscfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
15 Configuration registers. This device is used to unmask them prior to use.
19 const: st,stih407-irq-syscfg
22 description: Phandle to Cortex-A9 IRQ system config registers
25 st,irq-device:
27 $ref: /schemas/types.yaml#/definitions/uint32-array
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/linux/fs/fuse/
H A Ddev.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
46 return time_is_before_jiffies(req->create_time + fc->timeout.req_timeout); in fuse_request_expired()
63 * - check the fiq pending list
64 * - check the bg queue
65 * - check the fpq io and processing lists
70 * between lists, re-sent requests at the head of the pending list having a
79 struct fuse_iqueue *fiq = &fc->iq; in fuse_check_timeout() local
84 if (!atomic_read(&fc->num_waiting)) in fuse_check_timeout()
87 spin_lock(&fiq->lock); in fuse_check_timeout()
88 expired = fuse_request_expired(fc, &fiq->pending); in fuse_check_timeout()
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H A Dinode.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
85 sl->forget = fuse_alloc_forget(); in fuse_alloc_submount_lookup()
86 if (!sl->forget) in fuse_alloc_submount_lookup()
104 fi->i_time = 0; in fuse_alloc_inode()
105 fi->inval_mask = ~0; in fuse_alloc_inode()
106 fi->nodeid = 0; in fuse_alloc_inode()
107 fi->nlookup = 0; in fuse_alloc_inode()
108 fi->attr_version = 0; in fuse_alloc_inode()
109 fi->orig_ino = 0; in fuse_alloc_inode()
110 fi->state = 0; in fuse_alloc_inode()
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H A Dfuse_i.h3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
23 #include <linux/backing-dev.h>
38 /** Bias for fi->writectr, meaning new writepages must not be sent */
46 #define FUSE_NAME_MAX (PATH_MAX - 1)
130 /** The sticky bit in inode->i_mode may have been removed, so
146 /* Files usable in writepage. Protected by fi->lock */
162 /* waitq for direct-io completion */
274 /** RB node to be linked on fuse_conn->polled_files */
280 /** Does file hold a fi->iocachectr refcount? */
398 * FR_URING: request is handled through fuse-io-uring
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H A Ddev_uring.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2023-2024 DataDirect Networks.
17 "Enable userspace communication through io-uring");
39 pdu->ent = ring_ent; in uring_cmd_set_ring_ent()
47 return pdu->ent; in uring_cmd_to_ring_ent()
52 struct fuse_ring *ring = queue->ring; in fuse_uring_flush_bg()
53 struct fuse_conn *fc = ring->fc; in fuse_uring_flush_bg()
55 lockdep_assert_held(&queue->lock); in fuse_uring_flush_bg()
56 lockdep_assert_held(&fc->bg_lock); in fuse_uring_flush_bg()
61 * eliminates the need for remote queue wake-ups when global in fuse_uring_flush_bg()
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/linux/arch/arm/include/asm/
H A Decard.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * 11-12-1996 RMK Further minor improvements
11 * 12-09-1997 RMK Added interrupt enable/disable for card level
104 unsigned char fiqmask; /* FIQ mask */
106 unsigned long fiqoff; /* FIQ offset */
130 #define ecard_resource_start(ec,nr) ((ec)->resource[nr].start)
131 #define ecard_resource_end(ec,nr) ((ec)->resource[nr].end)
132 #define ecard_resource_len(ec,nr) ((ec)->resource[nr].end - \
133 (ec)->resource[nr].start + 1)
134 #define ecard_resource_flags(ec,nr) ((ec)->resource[nr].flags)
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/linux/arch/arm/mach-rpc/
H A Ddma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-rpc/dma.c
12 #include <linux/dma-mapping.h>
17 #include <asm/fiq.h>
48 #define ENDA (IOMD_IO0ENDA - IOMD_IO0CURA)
49 #define CURB (IOMD_IO0CURB - IOMD_IO0CURA)
50 #define ENDB (IOMD_IO0ENDB - IOMD_IO0CURA)
51 #define CR (IOMD_IO0CR - IOMD_IO0CURA)
52 #define ST (IOMD_IO0ST - IOMD_IO0CURA)
58 if (idma->dma.sg) { in iomd_get_next_sg()
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H A Decard.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 1995-2001 Russell King
11 * 08-Dec-1996 RMK Added code for the 9'th expansion card - the ether
13 * 06-May-1997 RMK Added blacklist for cards whose loader doesn't work.
14 * 12-Sep-1997 RMK Created new handling of interrupt enables/disables
15 * - cards can now register their own routine to control
17 * 29-Sep-1997 RMK Expansion card interrupt hardware not being re-enabled
20 * 15-Feb-1998 RMK Added DMA support
21 * 12-Sep-1998 RMK Added EASI support
22 * 10-Jan-1999 RMK Run loaders in a simulated RISC OS environment.
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/linux/drivers/irqchip/
H A Dirq-apple-aic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on irq-lpc32xx:
6 * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
7 * Based on irq-bcm2836:
14 * - 896 level-triggered hardware IRQs
15 * - Single mask bit per IRQ
16 * - Per-IRQ affinity setting
17 * - Automatic masking on event delivery (auto-ack)
18 * - Software triggering (ORed with hw line)
19 * - 2 per-CPU IPIs (meant as "self" and "other", but they are
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/linux/sound/soc/fsl/
H A Dimx-pcm-fiq.c1 // SPDX-License-Identifier: GPL-2.0+
2 // imx-pcm-fiq.c -- ALSA Soc Audio Layer
11 #include <linux/device.h>
12 #include <linux/dma-mapping.h>
26 #include <asm/fiq.h>
28 #include <linux/platform_data/asoc-imx-ssi.h>
30 #include "imx-ssi.h"
31 #include "imx-pcm.h"
48 struct snd_pcm_substream *substream = iprtd->substream; in snd_hrtimer_callback()
51 if (!atomic_read(&iprtd->playing) && !atomic_read(&iprtd->capturing)) in snd_hrtimer_callback()
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/linux/arch/arm64/kernel/
H A Dentry.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level exception handling code
10 #include <linux/arm-smccc.h>
16 #include <asm/asm-offsets.h>
30 #include <asm/asm-uaccess.h>
64 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
66 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
67 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
89 * after panic() re-enables interrupts.
93 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
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/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,ssi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
18 DMA controller to use, but the channels themselves are hard-wired. The
21 The device tree nodes for the DMA channels that are referenced by
22 "fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
23 "fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
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/linux/arch/arm/mach-imx/
H A Dtzic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 #include <linux/device.h>
20 #include "irq-common.h"
58 return -EINVAL; in tzic_set_irq_fiq()
76 int idx = d->hwirq >> 5; in tzic_irq_suspend()
78 imx_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx)); in tzic_irq_suspend()
83 int idx = d->hwirq >> 5; in tzic_irq_resume()
107 gc->private = &tzic_extra_irq; in tzic_init_gc()
108 gc->wake_enabled = IRQ_MSK(32); in tzic_init_gc()
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/linux/Documentation/arch/arm64/
H A Dbooting.rst13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
27 2. Setup the device tree
33 ---------------------------
48 2. Setup the device tree
49 -------------------------
53 The device tree blob (dtb) must be placed on an 8-byte boundary and must
62 ------------------------------
74 ------------------------
78 The decompressed kernel image contains a 64-byte header as follows::
94 - As of v3.17, all fields are little endian unless stated otherwise.
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/linux/arch/arm/mach-bcm/
H A Dbcm_kona_smc.c1 // SPDX-License-Identifier: GPL-2.0-only
25 {.compatible = "brcm,kona-smc"},
26 {.compatible = "bcm,kona-smc"}, /* deprecated name */
37 /* Read buffer addr and size from the device tree node */ in bcm_kona_smc_init()
40 return -ENODEV; in bcm_kona_smc_init()
45 return -EINVAL; in bcm_kona_smc_init()
49 return -ENOMEM; in bcm_kona_smc_init()
69 * Parameters to the "smc" request are passed in r4-r6 as follows:
96 r5 = 0x3; /* Keep IRQ and FIQ off in SM */ in bcm_kona_do_smc()
117 /* __bcm_kona_smc() should only run on CPU 0, with pre-emption disabled */
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/linux/Documentation/arch/arm/
H A Dtcm.rst2 ARM TCM (Tightly-Coupled Memory) handling in Linux
7 Some ARM SoCs have a so-called TCM (Tightly-Coupled Memory).
8 This is usually just a few (4-64) KiB of RAM inside the ARM
12 Harvard-architecture, so there is an ITCM (instruction TCM)
24 determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present
52 - FIQ and other interrupt handlers that need deterministic
55 - Idle loops where all external RAM is set to self-refresh
56 retention mode, so only on-chip RAM is accessible by
60 - Other operations which implies shutting off or reconfiguring
66 - Define the physical address and size of ITCM and DTCM.
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/linux/arch/arm64/include/asm/
H A Dkvm_arm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
96 * PTW: Take a stage2 fault if a stage1 walk steps in device memory
153 * We configure the Stage-2 page tables to always restrict the IPA space to be
172 * -----------------------------------------
174 * ------------------------------------------
175 * | Level: 0 | 2 | - |
176 * ------------------------------------------
178 * ------------------------------------------
180 * ------------------------------------------
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/linux/arch/arm/kernel/
H A Dsetup.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 1995-2001 Russell King
46 #include <asm/mach-types.h>
140 u32 fiq[4]; member
300 /* I-cache aliases will be handled by D-cache aliasing code */ in cpu_has_aliasing_icache()
353 * These functions re-use the assembly code in head.S, which
527 * cpu_init - initialise one CPU.
529 * cpu_init sets up the per-CPU stacks.
552 * In Thumb-2, msr with an immediate value is not allowed. in cpu_init()
563 * setup stacks for re-entrant exception handlers in cpu_init()
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/linux/arch/arm64/kvm/vgic/
H A Dvgic-v3.c1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/irqchip/arm-gic-v3.h>
25 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; in vgic_v3_set_underflow()
27 cpuif->vgic_hcr |= ICH_HCR_EL2_UIE; in vgic_v3_set_underflow()
38 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; in vgic_v3_fold_lr_state()
39 struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3; in vgic_v3_fold_lr_state()
40 u32 model = vcpu->kvm->arch.vgic.vgic_model; in vgic_v3_fold_lr_state()
45 cpuif->vgic_hcr &= ~ICH_HCR_EL2_UIE; in vgic_v3_fold_lr_state()
47 for (lr = 0; lr < cpuif->used_lrs; lr++) { in vgic_v3_fold_lr_state()
48 u64 val = cpuif->vgic_lr[lr]; in vgic_v3_fold_lr_state()
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/linux/arch/arm/boot/dts/st/
H A Dstih407-family.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-resets.h>
10 #include <dt-bindings/interrupt-controller/irq-st.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 reserved-memory {
16 #address-cells = <1>;
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