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/linux/Documentation/devicetree/bindings/clock/
H A Dnvidia,tegra124-car.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Clock and Reset Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The Clock and Reset (CAR) is the HW module responsible for muxing and gating
18 the clock source programming and most of the clock dividers.
20 CLKGEN input signals include the external clock for the reference frequency
[all …]
H A Dsamsung,exynos-ext-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos-ext-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC external/osc/XXTI/XusbXTI clock
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Samsung SoCs require an external clock supplied through XXTI or XusbXTI pins.
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H A Dsamsung,s5pv210-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5P6442/S5PC110/S5PV210 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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H A Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
16 connected with an external fixed rate oscillator, which signal is transformed
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
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H A Dpwm-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/pwm-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: An external clock signal driven by a PWM pin.
10 - Philipp Zabel <p.zabel@pengutronix.de>
14 const: pwm-clock
16 '#clock-cells':
19 clock-frequency:
20 description: Exact output frequency, in case the PWM period is not exact
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/linux/Documentation/devicetree/bindings/iio/imu/
H A Dadi,adis16480.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
15 - enum:
16 - adi,adis16375
17 - adi,adis16480
18 - adi,adis16485
19 - adi,adis16486
20 - adi,adis16488
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/linux/Documentation/devicetree/bindings/media/i2c/
H A Dtoshiba,et8ek8.txt6 Documentation/devicetree/bindings/media/video-interfaces.txt .
10 --------------------
12 - compatible: "toshiba,et8ek8"
13 - reg: I2C address (0x3e, or an alternative address)
14 - vana-supply: Analogue voltage supply (VANA), 2.8 volts
15 - clocks: External clock to the sensor
16 - clock-frequency: Frequency of the external clock to the sensor. Camera
17 driver will set this frequency on the external clock. The clock frequency is
18 a pre-determined frequency known to be suitable to the board.
19 - reset-gpios: XSHUTDOWN GPIO. The XSHUTDOWN signal is active low. The sensor
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H A Dmipi-ccs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2014--2020 Intel Corporation
4 ---
5 $id: http://devicetree.org/schemas/media/i2c/mipi-ccs.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sakari Ailus <sakari.ailus@linux.intel.com>
17 <URL:https://www.mipi.org/specifications/camera-command-set>.
24 Documentation/devicetree/bindings/media/video-interfaces.txt .
27 - $ref: /schemas/media/video-interface-devices.yaml#
32 - items:
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/linux/Documentation/devicetree/bindings/net/can/
H A Dcc770.txt8 - compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
11 - reg : should specify the chip select, address offset and size required
14 - interrupts : property with a value describing the interrupt source
19 - bosch,external-clock-frequency : frequency of the external oscillator
20 clock in Hz. Note that the internal clock frequency used by the
24 - bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
28 - bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
31 - bosch,disconnect-rx0-input : see data sheet.
33 - bosch,disconnect-rx1-input : see data sheet.
35 - bosch,disconnect-tx1-output : see data sheet.
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H A Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - const: renesas,r9a06g032-sja1000 # RZ/N1D
20 - const: renesas,rzn1-sja1000 # RZ/N1
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/linux/drivers/media/i2c/
H A Dccs-pll.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * drivers/media/i2c/ccs-pll.h
17 /* CSI-2 or CCP-2 */
22 /* OP PIX clock is for all lanes in total normally. */
33 /* If set, the pre-PLL divider may have odd values, too. */
36 * If set, the OP PIX clock doesn't have to exactly match with data rate, it may
47 * If set, the OP SYS clock is a dual data rate clock, transferring two bits per
52 * If set, the OP PIX clock is a dual data rate clock, transferring two pixels
58 * struct ccs_pll_branch_fr - CCS PLL configuration (front)
60 * A single branch front-end of the CCS PLL tree.
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/linux/Documentation/devicetree/bindings/spi/
H A Dnxp,sc18is.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 - nxp,sc18is602
16 - nxp,sc18is602b
17 - nxp,sc18is603
22 clock-frequency:
26 external oscillator clock frequency. The clock-frequency property is
27 relevant and needed only if the chip has an external oscillator
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/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,adrf6780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/frequency/adi,adrf6780.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
14 radio designs operating in the 5.9 GHz to 23.6 GHz frequency range.
21 - adi,adrf6780
26 spi-max-frequency:
31 Definition of the external clock.
34 clock-names:
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/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-common.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
9 #include "jh7110-pinfunc.h"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
27 stdout-path = "serial0:115200n8";
33 bootph-pre-ram;
36 gpio-restart {
37 compatible = "gpio-restart";
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/linux/Documentation/devicetree/bindings/ptp/
H A Dfsl,ptp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QorIQ 1588 timer based PTP clock
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,etsec-ptp
17 - fsl,fman-ptp-timer
18 - fsl,dpaa2-ptp
19 - items:
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/linux/Documentation/driver-api/
H A Dptp.rst1 .. SPDX-License-Identifier: GPL-2.0
4 PTP hardware clock infrastructure for Linux
10 programs, synchronizing Linux with external clocks, and using the
13 A new class driver exports a kernel interface for specific clock
15 complete set of PTP hardware clock functionality.
17 + Basic clock operations
18 - Set time
19 - Get time
20 - Shift the clock by a given offset atomically
21 - Adjust clock frequency
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/linux/drivers/clk/analogbits/
H A Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
13 * The bulk of this code is primarily useful for clock configurations
14 * that must operate at arbitrary rates, as opposed to clock configurations
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
33 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
35 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
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/linux/arch/xtensa/boot/dts/
H A Dxtfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 compatible = "cdns,xtensa-xtfpga";
4 #address-cells = <1>;
5 #size-cells = <1>;
6 interrupt-parent = <&pic>;
18 #address-cells = <1>;
19 #size-cells = <0>;
21 compatible = "cdns,xtensa-cpu";
28 compatible = "cdns,xtensa-pic";
31 * second cell == 1: external irq number
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/linux/Documentation/devicetree/bindings/mips/cavium/
H A Ductl.txt4 - compatible: "cavium,octeon-6335-uctl"
8 - reg: The base address of the UCTL register bank.
10 - #address-cells: Must be <2>.
12 - #size-cells: Must be <2>.
14 - ranges: Empty to signify direct mapping of the children.
16 - refclk-frequency: A single cell containing the reference clock
17 frequency in Hz.
19 - refclk-type: A string describing the reference clock connection
20 either "crystal" or "external".
24 compatible = "cavium,octeon-6335-uctl";
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/linux/Documentation/devicetree/bindings/media/
H A Dnxp,imx-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <rmfrfs@gmail.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 description: |-
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
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/linux/Documentation/devicetree/bindings/net/ieee802154/
H A Dca8210.txt4 - compatible: Should be "cascoda,ca8210"
5 - reg: Controlling chip select
6 - spi-max-frequency: Maximum clock speed, should be *less than*
8 - spi-cpol: Requires inverted clock polarity
9 - reset-gpio: GPIO attached to reset
10 - irq-gpio: GPIO attached to IRQ
12 - extclock-enable: Include for the ca8210 to route its 16MHz clock
14 - extclock-freq: Frequency in Hz of the external clock
15 - extclock-gpio: GPIO of the ca8210 to output the clock on
21 spi-max-frequency = <3000000>;
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/linux/drivers/media/dvb-frontends/
H A Dlgs8gxx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Support for Legend Silicon GB20600 (a.k.a DMB-TH) demodulator
7 * Copyright (C) 2007-2009 David T.L. Wong <davidtlwong@gmail.com>
39 /* transport stream clock gated by ts_valid */
42 /* A/D Clock frequency */
45 /* IF frequency */
48 /*Use External ADC*/
51 /*External ADC output two's complement*/
57 /*IF use Negative center frequency*/
/linux/arch/powerpc/boot/dts/
H A Dtqm8xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <16>; // 16 bytes
32 i-cache-line-size = <16>; // 16 bytes
33 d-cache-size = <0x1000>; // L1, 4K
34 i-cache-size = <0x1000>; // L1, 4K
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/linux/Documentation/devicetree/bindings/iio/filter/
H A Dadi,admv8818.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ADMV8818 Digitally Tunable, High-Pass and Low-Pass Filter
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
14 features a digitally selectable frequency of operation.
15 The device features four independently controlled high-pass
16 filters (HPFs) and four independently controlled low-pass filters
17 (LPFs) that span the 2 GHz to 18 GHz frequency range.
24 - adi,admv8818
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q-skov-reve-mi1010ait-1cp1.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 /dts-v1/;
7 #include "imx6qdl-skov-cpu.dtsi"
11 compatible = "skov,imx6q-skov-reve-mi1010ait-1cp1", "fsl,imx6q";
14 compatible = "pwm-backlight";
15 pinctrl-names = "default";
16 pinctrl-0 = <&pinctrl_backlight>;
17 enable-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>;
19 brightness-levels = <0 255>;
20 num-interpolated-steps = <17>;
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