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/linux/tools/perf/util/
H A Dcs-etm.c22 #include "cs-etm.h"
23 #include "cs-etm-decoder/cs-etm-decoder.h"
107 struct cs_etm_auxtrace *etm; member
129 static int cs_etm__process_timestamped_queues(struct cs_etm_auxtrace *etm);
130 static int cs_etm__process_timeless_queues(struct cs_etm_auxtrace *etm,
135 static u64 *get_cpu_data(struct cs_etm_auxtrace *etm, int cpu);
144 * encode the etm queue number as the upper 16 bit and the channel as
204 * The result is cached in etm->pid_fmt so this function only needs to be called
231 return etmq->etm in cs_etm__get_pid_fmt()
284 cs_etm__get_queue(struct cs_etm_auxtrace * etm,int cpu) cs_etm__get_queue() argument
292 cs_etm__map_trace_id_v0(struct cs_etm_auxtrace * etm,u8 trace_chan_id,u64 * cpu_metadata) cs_etm__map_trace_id_v0() argument
323 cs_etm__process_trace_id_v0(struct cs_etm_auxtrace * etm,int cpu,u64 hw_id) cs_etm__process_trace_id_v0() argument
345 cs_etm__process_trace_id_v0_1(struct cs_etm_auxtrace * etm,int cpu,u64 hw_id) cs_etm__process_trace_id_v0_1() argument
449 get_cpu_data_idx(struct cs_etm_auxtrace * etm,int cpu) get_cpu_data_idx() argument
466 get_cpu_data(struct cs_etm_auxtrace * etm,int cpu) get_cpu_data() argument
483 struct cs_etm_auxtrace *etm; cs_etm__process_aux_output_hw_id() local
612 struct cs_etm_auxtrace *etm = etmq->etm; cs_etm__init_traceid_queue() local
666 struct cs_etm_auxtrace *etm = etmq->etm; cs_etm__etmq_get_traceid_queue() local
744 cs_etm__packet_swap(struct cs_etm_auxtrace * etm,struct cs_etm_traceid_queue * tidq) cs_etm__packet_swap() argument
907 struct cs_etm_auxtrace *etm = container_of(session->auxtrace, cs_etm__flush_events() local
1190 cs_etm__setup_queue(struct cs_etm_auxtrace * etm,struct auxtrace_queue * queue,unsigned int queue_nr) cs_etm__setup_queue() argument
1214 cs_etm__queue_first_cs_timestamp(struct cs_etm_auxtrace * etm,struct cs_etm_queue * etmq,unsigned int queue_nr) cs_etm__queue_first_cs_timestamp() argument
1543 struct cs_etm_auxtrace *etm = etmq->etm; cs_etm__convert_sample_time() local
1554 struct cs_etm_auxtrace *etm = etmq->etm; cs_etm__resolve_sample_time() local
1568 struct cs_etm_auxtrace *etm = etmq->etm; cs_etm__synth_instruction_sample() local
1621 struct cs_etm_auxtrace *etm = etmq->etm; cs_etm__synth_branch_sample() local
1687 cs_etm__synth_events(struct cs_etm_auxtrace * etm,struct perf_session * session) cs_etm__synth_events() argument
1775 struct cs_etm_auxtrace *etm = etmq->etm; cs_etm__sample() local
1924 struct cs_etm_auxtrace *etm = etmq->etm; cs_etm__flush() local
2588 cs_etm__process_timeless_queues(struct cs_etm_auxtrace * etm,pid_t tid) cs_etm__process_timeless_queues() argument
2618 cs_etm__process_timestamped_queues(struct cs_etm_auxtrace * etm) cs_etm__process_timestamped_queues() argument
2748 cs_etm__process_itrace_start(struct cs_etm_auxtrace * etm,union perf_event * event) cs_etm__process_itrace_start() argument
2773 cs_etm__process_switch_cpu_wide(struct cs_etm_auxtrace * etm,union perf_event * event) cs_etm__process_switch_cpu_wide() argument
2816 struct cs_etm_auxtrace *etm = container_of(session->auxtrace, cs_etm__process_event() local
2866 dump_queued_data(struct cs_etm_auxtrace * etm,struct perf_record_auxtrace * event) dump_queued_data() argument
2886 struct cs_etm_auxtrace *etm = container_of(session->auxtrace, cs_etm__process_auxtrace_event() local
2921 cs_etm__setup_timeless_decoding(struct cs_etm_auxtrace * etm) cs_etm__setup_timeless_decoding() argument
3028 struct cs_etm_auxtrace *etm = container_of(session->auxtrace, cs_etm__queue_aux_fragment() local
3247 cs_etm__map_trace_ids_metadata(struct cs_etm_auxtrace * etm,int num_cpu,u64 ** metadata) cs_etm__map_trace_ids_metadata() argument
3337 cs_etm__create_decoders(struct cs_etm_auxtrace * etm) cs_etm__create_decoders() argument
3365 struct cs_etm_auxtrace *etm = NULL; cs_etm__process_auxtrace_info_full() local
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/linux/Documentation/devicetree/bindings/arm/
H A Dqcom,coresight-remote-etm.yaml4 $id: http://devicetree.org/schemas/arm/qcom,coresight-remote-etm.yaml#
7 title: Qualcomm Coresight Remote ETM(Embedded Trace Macrocell)
14 Support for ETM trace collection on remote processor using coresight
15 framework. Enabling this will allow turning on ETM tracing on remote
21 const: qcom,coresight-remote-etm
40 etm {
41 compatible = "qcom,coresight-remote-etm";
H A Darm,coresight-etm.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml#
23 The Embedded Trace Macrocell (ETM) is a real-time trace module providing
91 Must be present if the system accesses ETM/PTM management registers via
105 phandle to the cpu this ETM is bound to.
114 description: Output connection from the ETM to CoreSight Trace bus.
H A Darm,coresight-cti.yaml32 architecture core and optional ETM.
35 between CTI and the CPU core and ETM if present. In the case of a v8
251 # v8 architecturally defined CTI - CPU + ETM connections generated by the
265 # Implementation defined CTI - CPU + ETM connections explicitly defined..
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/
H A Detm.json3 "PublicDescription": "ETM trace unit output 0",
6 "BriefDescription": "ETM trace unit output 0"
9 "PublicDescription": "ETM trace unit output 1",
12 "BriefDescription": "ETM trace unit output 1"
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
H A Detm.json3 "PublicDescription": "ETM trace unit output 0",
6 "BriefDescription": "ETM trace unit output 0"
9 "PublicDescription": "ETM trace unit output 1",
12 "BriefDescription": "ETM trace unit output 1"
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A Dcore-imp-def.json117 "PublicDescription": "ETM extout bit 0",
120 "BriefDescription": "ETM extout bit 0"
123 "PublicDescription": "ETM extout bit 1",
126 "BriefDescription": "ETM extout bit 1"
129 "PublicDescription": "ETM extout bit 2",
132 "BriefDescription": "ETM extout bit 2"
135 "PublicDescription": "ETM extout bit 3",
138 "BriefDescription": "ETM extout bit 3"
459 "PublicDescription": "Counts cycles that MSC is telling GPC to stall commit due to ETM ISTALL feature",
462 "BriefDescription": "Counts cycles that MSC is telling GPC to stall commit due to ETM ISTAL
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/linux/drivers/hwtracing/coresight/
H A Dcoresight-etm.h144 * struct etm_config - configuration information related to an ETM
145 * @mode: controls various modes supported by this ETM/PTM.
209 * struct etm_drvdata - specifics associated to an ETM component
211 * @atclk: optional clock for the core parts of the ETM.
216 * @arch: ETM/PTM version number.
218 * @sticky_enable: true if ETM base configuration has been done.
260 "invalid CP14 access to ETM reg: %#x", off); in etm_writel()
274 "invalid CP14 access to ETM reg: %#x", off); in etm_readl()
H A Dcoresight-etm3x-core.c33 #include "coresight-etm.h"
34 #include "coresight-etm-perf.h"
111 * @drvdata: etm's private data structure.
349 * Possible to have cores with PTM (supports ret stack) and ETM in etm_parse_event_config()
491 * Configure the ETM only if the CPU is online. If it isn't online in etm_enable_sysfs()
512 dev_dbg(&csdev->dev, "ETM tracing enabled\n"); in etm_enable_sysfs()
606 * DYING hotplug callback is serviced by the ETM driver. in etm_disable_sysfs()
612 * Executing etm_disable_hw on the cpu whose ETM is being disabled in etm_disable_sysfs()
627 dev_dbg(&csdev->dev, "ETM tracing disabled\n"); in etm_disable_sysfs()
740 /* Provide power to ETM in etm_init_arch_data()
[all...]
H A Dcoresight-etm-perf.c23 #include "coresight-etm-perf.h"
32 * An ETM context for a running event includes the perf aux handle
33 * and aux_data. For ETM, the aux_data (etm_event_data), consists of
42 * the ETM. Thus the event_data for the session must be part of the ETM context
348 * trace path for each CPU in the mask. If we don't find an ETM in etm_setup_aux()
359 * If there is no ETM associated with this CPU clear it from in etm_setup_aux()
369 * If AUX pause feature is enabled but the ETM driver does not in etm_setup_aux()
394 /* Find the default sink for this ETM */ in etm_setup_aux()
489 dev_err(&csdev->dev, "Failed to resume ETM even in etm_event_start()
[all...]
H A DKconfig95 the ETM version data tracing may also be available.
115 bool "Control implementation defined overflow support in ETM 4.x driver"
119 ETM 4.x tracer module that can't reduce commit rate automatically.
120 This avoids overflow between the ETM tracer module and the cpu core.
223 SMB is responsible for receiving the trace data from Coresight ETM devices
H A Dcoresight-cti-platform.c127 /* Can optionally have an etm node - return if not */ in cti_plat_create_v8_etm_connection()
143 * The EXTOUT type signals from the ETM are connected to a set of input in cti_plat_create_v8_etm_connection()
152 * We look to see if the ETM coresight device associated with this in cti_plat_create_v8_etm_connection()
158 * probing of the ETM will call into the CTI driver API to update the in cti_plat_create_v8_etm_connection()
171 * must have a cpu, can have an ETM.
210 /* Create the v8 ETM associated connection */ in cti_plat_create_v8_connections()
H A Dcoresight-etm4x.h228 * System instructions to access ETM registers.
644 * Bit[15:0] - ARCHID, Identifies this component as an ETM
645 * * Bits[15:12] - architecture version of ETM
647 * * Bits[11:0] = 0xA13, architecture part number for ETM.
695 * ETM defines the bits for EL control (e.g, TRVICTLR, TRCACTRn).
728 * Driver representation of the ETM architecture.
729 * The version of an ETM component can be detected from
756 /* Interpretation of resource numbers change at ETM v4.3 architecture */
772 * @mode: Controls various modes supported by this ETM.
865 * struct etm4_save_state - state to be preserved when ETM i
[all...]
H A DMakefile28 coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
40 coresight-etm3x-y := coresight-etm3x-core.o coresight-etm-cp14.o \
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3660-coresight.dtsi14 etm@ecc40000 {
32 etm@ecd40000 {
50 etm@ece40000 {
68 etm@ecf40000 {
161 etm@ed440000 {
179 etm@ed540000 {
197 etm@ed640000 {
215 etm@ed740000 {
H A Dhi6220-coresight.dtsi216 etm0: etm@f659c000 {
235 etm1: etm@f659d000 {
254 etm2: etm@f659e000 {
273 etm3: etm@f659f000 {
292 etm4: etm@f65dc000 {
311 etm5: etm@f65dd000 {
330 etm6: etm@f65de000 {
349 etm7: etm@f65df000 {
/linux/drivers/clk/mxs/
H A Dclk-imx23.c34 #define ETM (CLKCTRL + 0x00e0) macro
86 lcdif, etm, usb, usb_phy, enumerator
134 clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 6, 29); in mx23_clocks_init()
151 clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31); in mx23_clocks_init()
H A Dclk-imx28.c37 #define ETM (CLKCTRL + 0x0130) macro
140 ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm, enumerator
202 clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29); in mx28_clocks_init()
223 clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31); in mx28_clocks_init()
/linux/arch/arm64/boot/dts/sprd/
H A Dsc9863a.dtsi412 etm@13040000 {
429 etm@13140000 {
446 etm@13240000 {
463 etm@13340000 {
480 etm@13440000 {
497 etm@13540000 {
514 etm@13640000 {
531 etm@13740000 {
H A Dsc9836.dtsi117 etm@10440000 {
133 etm@10540000 {
149 etm@10640000 {
165 etm@10740000 {
H A Dsc9860.dtsi551 etm@11440000 {
568 etm@11540000 {
585 etm@11640000 {
602 etm@11740000 {
619 etm@11840000 {
636 etm@11940000 {
653 etm@11a40000 {
670 etm@11b40000 {
H A Dums512.dtsi688 etm0: etm@3f040000 {
705 etm1: etm@3f140000 {
722 etm2: etm@3f240000 {
739 etm3: etm@3f340000 {
756 etm4: etm@3f440000 {
773 etm5: etm@3f540000 {
790 etm6: etm@3f640000 {
807 etm7: etm@3f740000 {
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereone/
H A Dcore-imp-def.json117 "PublicDescription": "ETM extout bit 0",
120 "BriefDescription": "ETM extout bit 0"
123 "PublicDescription": "ETM extout bit 1",
126 "BriefDescription": "ETM extout bit 1"
129 "PublicDescription": "ETM extout bit 2",
132 "BriefDescription": "ETM extout bit 2"
135 "PublicDescription": "ETM extout bit 3",
138 "BriefDescription": "ETM extout bit 3"
/linux/tools/perf/arch/arm/util/
H A Dpmu.c16 #include "../../../util/cs-etm.h"
25 /* add ETM default config here */ in perf_pmu__arch_init()
/linux/include/linux/
H A Dcoresight-pmu.h26 * arbitrary values for all ETM versions.
39 /* ETMv4 CONFIGR programming bits for the ETM OPTs */

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