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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-tf300t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-displa
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H A Dtegra124-jetson-tk1-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
7 emc-timings-3 {
8 nvidia,ram-code = <3>;
10 timing-1275000
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H A Dtegra124-apalis-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
7 #include <dt-bindings/clock/tegra124-car.h>
11 emc-timings-1 {
12 nvidia,ram-cod
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H A Dtegra30-asus-tf300tg.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-displa
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H A Dtegra124-nyan-blaze-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
7 emc-timings-1 {
8 nvidia,ram-code = <1>;
10 timing-1275000
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H A Dtegra30-asus-tf700t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
20 remote-endpoint = <&bridge_input>;
21 bus-width = <24>;
36 nvidia,enable-inpu
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H A Dtegra30-asus-tf201.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-displa
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H A Dtegra30-asus-tf300tl.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-displa
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H A Dtegra30-lg-p880.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-lg-x3.dtsi"
16 pinctrl-names = "default";
17 pinctrl-0 = <&state_default>;
21 host-wlan-wak
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H A Dtegra30-lg-p895.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-lg-x3.dtsi"
11 pinctrl-names = "default";
12 pinctrl-0 = <&state_default>;
15 /* GNSS UART-B pinmux */
16 uartb-ct
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H A Dtegra124-nyan-big-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
7 emc-timings-1 {
8 nvidia,ram-code = <1>;
10 timing-1275000
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H A Dtegra30-asus-nexus7-grouper-memory-timings.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 memory-controller@7000f000 {
5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-
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H A Dtegra30-asus-tf600t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-cp
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H A Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "tegra30-asus-nexus7-grouper-memory-timings.dtsi"
12 memory-controller@7000f400 {
13 emc
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H A Dtegra30-asus-p1801-t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-op
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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controller
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H A Dnvidia,tegra30-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schema
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/linux/drivers/memory/tegra/
H A Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
15 #include <linux/interconnect-provider.h>
507 * There are multiple sources in the EMC driver which could request
512 /* protect shared rate-change code path */
518 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
521 writel(value, emc in emc_ccfifo_writel()
525 emc_seq_update_timing(struct tegra_emc * emc) emc_seq_update_timing() argument
542 emc_seq_disable_auto_cal(struct tegra_emc * emc) emc_seq_disable_auto_cal() argument
559 emc_seq_wait_clkchange(struct tegra_emc * emc) emc_seq_wait_clkchange() argument
574 tegra_emc_find_timing(struct tegra_emc * emc,unsigned long rate) tegra_emc_find_timing() argument
595 tegra_emc_prepare_timing_change(struct tegra_emc * emc,unsigned long rate) tegra_emc_prepare_timing_change() argument
823 tegra_emc_complete_timing_change(struct tegra_emc * emc,unsigned long rate) tegra_emc_complete_timing_change() argument
880 emc_read_current_timing(struct tegra_emc * emc,struct emc_timing * timing) emc_read_current_timing() argument
899 emc_init(struct tegra_emc * emc) emc_init() argument
920 load_one_timing_from_dt(struct tegra_emc * emc,struct emc_timing * timing,struct device_node * node) load_one_timing_from_dt() argument
991 tegra_emc_load_timings_from_dt(struct tegra_emc * emc,struct device_node * node) tegra_emc_load_timings_from_dt() argument
1046 tegra_emc_rate_requests_init(struct tegra_emc * emc) tegra_emc_rate_requests_init() argument
1056 emc_request_rate(struct tegra_emc * emc,unsigned long new_min_rate,unsigned long new_max_rate,enum emc_rate_request_type type) emc_request_rate() argument
1097 emc_set_min_rate(struct tegra_emc * emc,unsigned long rate,enum emc_rate_request_type type) emc_set_min_rate() argument
1110 emc_set_max_rate(struct tegra_emc * emc,unsigned long rate,enum emc_rate_request_type type) emc_set_max_rate() argument
1148 tegra_emc_validate_rate(struct tegra_emc * emc,unsigned long rate) tegra_emc_validate_rate() argument
1162 struct tegra_emc *emc = s->private; tegra_emc_debug_available_rates_show() local
1180 struct tegra_emc *emc = data; tegra_emc_debug_min_rate_get() local
1189 struct tegra_emc *emc = data; tegra_emc_debug_min_rate_set() local
1210 struct tegra_emc *emc = data; tegra_emc_debug_max_rate_get() local
1219 struct tegra_emc *emc = data; tegra_emc_debug_max_rate_set() local
1238 emc_debugfs_init(struct device * dev,struct tegra_emc * emc) emc_debugfs_init() argument
1315 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); emc_icc_set() local
1339 tegra_emc_interconnect_init(struct tegra_emc * emc) tegra_emc_interconnect_init() argument
1392 tegra_emc_opp_table_init(struct tegra_emc * emc) tegra_emc_opp_table_init() argument
1442 struct tegra_emc *emc; tegra_emc_probe() local
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H A Dtegra30-emc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
18 #include <linux/interconnect-provider.h>
387 * There are multiple sources in the EMC driver which could request
392 /* protect shared rate-chang
398 emc_seq_update_timing(struct tegra_emc * emc) emc_seq_update_timing() argument
418 struct tegra_emc *emc = data; tegra_emc_isr() local
437 emc_find_timing(struct tegra_emc * emc,unsigned long rate) emc_find_timing() argument
458 emc_dqs_preset(struct tegra_emc * emc,struct emc_timing * timing,bool * schmitt_to_vref) emc_dqs_preset() argument
501 emc_prepare_mc_clk_cfg(struct tegra_emc * emc,unsigned long rate) emc_prepare_mc_clk_cfg() argument
523 emc_prepare_timing_change(struct tegra_emc * emc,unsigned long rate) emc_prepare_timing_change() argument
792 emc_complete_timing_change(struct tegra_emc * emc,unsigned long rate) emc_complete_timing_change() argument
843 emc_unprepare_timing_change(struct tegra_emc * emc,unsigned long rate) emc_unprepare_timing_change() argument
858 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb); emc_clk_change_notify() local
888 load_one_timing_from_dt(struct tegra_emc * emc,struct emc_timing * timing,struct device_node * node) load_one_timing_from_dt() argument
956 emc_check_mc_timings(struct tegra_emc * emc) emc_check_mc_timings() argument
979 emc_load_timings_from_dt(struct tegra_emc * emc,struct device_node * node) emc_load_timings_from_dt() argument
1023 emc_find_node_by_ram_code(struct tegra_emc * emc) emc_find_node_by_ram_code() argument
1056 emc_read_lpddr_mode_register(struct tegra_emc * emc,unsigned int emem_dev,unsigned int register_addr,unsigned int * register_data) emc_read_lpddr_mode_register() argument
1092 emc_read_lpddr_sdram_info(struct tegra_emc * emc,unsigned int emem_dev) emc_read_lpddr_sdram_info() argument
1115 emc_setup_hw(struct tegra_emc * emc) emc_setup_hw() argument
1196 struct tegra_emc *emc = arg; emc_round_rate() local
1231 tegra_emc_rate_requests_init(struct tegra_emc * emc) tegra_emc_rate_requests_init() argument
1241 emc_request_rate(struct tegra_emc * emc,unsigned long new_min_rate,unsigned long new_max_rate,enum emc_rate_request_type type) emc_request_rate() argument
1282 emc_set_min_rate(struct tegra_emc * emc,unsigned long rate,enum emc_rate_request_type type) emc_set_min_rate() argument
1295 emc_set_max_rate(struct tegra_emc * emc,unsigned long rate,enum emc_rate_request_type type) emc_set_max_rate() argument
1333 tegra_emc_validate_rate(struct tegra_emc * emc,unsigned long rate) tegra_emc_validate_rate() argument
1346 struct tegra_emc *emc = s->private; tegra_emc_debug_available_rates_show() local
1363 struct tegra_emc *emc = data; tegra_emc_debug_min_rate_get() local
1372 struct tegra_emc *emc = data; tegra_emc_debug_min_rate_set() local
1393 struct tegra_emc *emc = data; tegra_emc_debug_max_rate_get() local
1402 struct tegra_emc *emc = data; tegra_emc_debug_max_rate_set() local
1421 tegra_emc_debugfs_init(struct tegra_emc * emc) tegra_emc_debugfs_init() argument
1498 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); emc_icc_set() local
1521 tegra_emc_interconnect_init(struct tegra_emc * emc) tegra_emc_interconnect_init() argument
1581 struct tegra_emc *emc = data; devm_tegra_emc_unreg_clk_notifier() local
1586 tegra_emc_init_clk(struct tegra_emc * emc) tegra_emc_init_clk() argument
1621 struct tegra_emc *emc; tegra_emc_probe() local
1692 struct tegra_emc *emc = dev_get_drvdata(dev); tegra_emc_suspend() local
1713 struct tegra_emc *emc = dev_get_drvdata(dev); tegra_emc_resume() local
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/linux/drivers/memory/
H A Dpl172.c1 // SPDX-License-Identifier: GPL-2.0
9 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
69 dev_err(&adev->dev, "%s timing too tight\n", name); in pl172_timing_prop()
70 return -EINVAL; in pl172_timing_prop()
73 writel(cycles, pl172->base + reg_offset); in pl172_timing_prop()
76 dev_dbg(&adev->de in pl172_timing_prop()
86 u32 cfg; pl172_setup_static() local
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/linux/drivers/pinctrl/
H A Dpinctrl-ingenic.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <linux/pinctrl/pinconf-generic.h>
177 (!(enabled_socs & GENMASK(version - 1, 0)) in is_soc_or_above()
178 || jzpc->info->version >= version); in is_soc_or_above()
224 INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1),
225 INGENIC_PIN_GROUP("mmc-
4261 unsigned int cfg, arg; ingenic_pinconf_set() local
4600 IF_ENABLED(cfg,ptr) global() argument
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/linux/drivers/clk/sprd/
H A Dsc9863a-clk.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9863a-clk.h>
26 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x94,
28 static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gat
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H A Dums512-clk.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/sprd,ums512-clk.h>
33 static CLK_FIXED_FACTOR_FW_NAME(clk_26m_aud, "clk-26m-aud", "ext-26m", 1, 1, 0);
34 static CLK_FIXED_FACTOR_FW_NAME(clk_13m, "clk-1
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/linux/drivers/clk/tegra/
H A Dclk-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2020 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/tegra210-car.h>
18 #include <dt-bindings/reset/tegra210-ca
275 sdin_get_n_eff(cfg) global() argument
1431 tegra210_pllx_dyn_ramp(struct tegra_clk_pll * pllx,struct tegra_clk_pll_freq_table * cfg) tegra210_pllx_dyn_ramp() argument
1479 tegra210_pll_fixed_mdiv_cfg(struct clk_hw * hw,struct tegra_clk_pll_freq_table * cfg,unsigned long rate,unsigned long input_rate) tegra210_pll_fixed_mdiv_cfg() argument
1548 tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table * cfg) tegra210_clk_pll_set_gain() argument
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/linux/drivers/ata/
H A Dsata_mv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * sata_mv.c - Marvell SATA support
5 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
6 * Copyright 2005: EMC Corporation, all rights reserved.
12 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
18 * --> Develo
1568 u32 cfg; mv_edma_cfg() local
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