Searched +full:emc +full:- +full:cfg +full:- +full:dyn +full:- +full:self +full:- +full:ref (Results 1 – 3 of 3) sorted by relevance
| /linux-5.10/arch/arm/boot/dts/ |
| D | tegra30-asus-nexus7-grouper-memory-timings.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 memory-controller@7000f000 {
5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
8 timing-25500000 {
9 clock-frequency = <25500000>;
11 nvidia,emem-configuration = <
33 timing-51000000 {
34 clock-frequency = <51000000>;
36 nvidia,emem-configuration = <
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| /linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra30-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
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| /linux-5.10/drivers/memory/tegra/ |
| D | tegra30-emc.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
357 static int emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
362 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
364 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
368 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
377 struct tegra_emc *emc = data; in tegra_emc_isr() local
381 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
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