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Searched full:eiointc (Results 1 – 11 of 11) sorted by relevance

/linux/arch/loongarch/kvm/intc/
H A Deiointc.c162 struct loongarch_eiointc *eiointc = vcpu->kvm->arch.eiointc; in kvm_eiointc_read() local
164 if (!eiointc) { in kvm_eiointc_read()
165 kvm_err("%s: eiointc irqchip not valid!\n", __func__); in kvm_eiointc_read()
170 kvm_err("%s: eiointc not aligned addr %llx len %d\n", __func__, addr, len); in kvm_eiointc_read()
177 spin_lock_irqsave(&eiointc->lock, flags); in kvm_eiointc_read()
178 ret = loongarch_eiointc_read(vcpu, eiointc, addr, &data); in kvm_eiointc_read()
179 spin_unlock_irqrestore(&eiointc->lock, flags); in kvm_eiointc_read()
298 struct loongarch_eiointc *eiointc = vcpu->kvm->arch.eiointc; in kvm_eiointc_write() local
300 if (!eiointc) { in kvm_eiointc_write()
301 kvm_err("%s: eiointc irqchip not valid!\n", __func__); in kvm_eiointc_write()
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H A Dpch_pic.c11 /* update the isr according to irq level and route irq to eiointc */
17 * set isr and route irq to eiointc and in pch_pic_update_irq()
24 eiointc_set_irq(s->kvm->arch.eiointc, irq, level); in pch_pic_update_irq()
30 eiointc_set_irq(s->kvm->arch.eiointc, irq, level); in pch_pic_update_irq()
77 eiointc_set_irq(kvm->arch.eiointc, irq, level); in pch_msi_set_irq()
165 /* only route to int0: eiointc */ in loongarch_pch_pic_read()
270 /* only route to int0: eiointc */ in loongarch_pch_pic_write()
274 /* route table to eiointc */ in loongarch_pch_pic_write()
/linux/Documentation/arch/loongarch/
H A Dirq-chip-model.rst9 Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
70 | EIOINTC | | LIOINTC | <-- | UARTs |
93 devices interrupts go to PCH-PIC/PCH-MSI and gathered by V-EIOINTC (Virtual
102 | V-EIOINTC |
118 V-EIOINTC (Virtual Extended I/O Interrupt Controller) is an extension of
119 EIOINTC, it only works in VM mode which runs in KVM hypervisor. Interrupts can
120 be routed to up to four vCPUs via standard EIOINTC, however with V-EIOINTC
123 With standard EIOINTC, interrupt routing setting includes two parts: eight
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/linux/arch/loongarch/boot/dts/
H A Dloongson-2k0500.dtsi90 interrupt-parent = <&eiointc>;
100 interrupt-parent = <&eiointc>;
110 interrupt-parent = <&eiointc>;
120 interrupt-parent = <&eiointc>;
163 eiointc: interrupt-controller@1fe11600 { label
164 compatible = "loongson,ls2k0500-eiointc";
353 interrupt-parent = <&eiointc>;
361 interrupt-parent = <&eiointc>;
369 interrupt-parent = <&eiointc>;
386 interrupt-parent = <&eiointc>;
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dloongson,eiointc.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,eiointc.yaml#
23 - loongson,ls2k0500-eiointc
24 - loongson,ls2k2000-eiointc
48 eiointc: interrupt-controller@1fe11600 {
49 compatible = "loongson,ls2k0500-eiointc";
/linux/Documentation/translations/zh_CN/arch/loongarch/
H A Dirq-chip-model.rst14 Legacy I/O Interrupt Controller）、EIOINTC（Extended I/O Interrupt Controller）、
18 CPUINTC是一种CPU内部的每个核本地的中断控制器，LIOINTC/EIOINTC/HTVECINTC是CPU内部的
72 | EIOINTC | | LIOINTC | <-- | UARTs |
103 | V-EIOINTC |
116 V-EIOINTC 是EIOINTC的扩展, 仅工作在虚拟机模式下, 中断经EIOINTC最多可个路由到
159 | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
192 EIOINTC::
241 - EIOINTC：即《龙芯3A5000处理器使用手册》第11.2节所描述的“扩展I/O中断”；
/linux/Documentation/translations/zh_TW/arch/loongarch/
H A Dirq-chip-model.rst14 Legacy I/O Interrupt Controller）、EIOINTC（Extended I/O Interrupt Controller）、
18 CPUINTC是一種CPU內部的每個核本地的中斷控制器，LIOINTC/EIOINTC/HTVECINTC是CPU內部的
72 | EIOINTC | | LIOINTC | <-- | UARTs |
105 EIOINTC::
154 - EIOINTC：即《龍芯3A5000處理器使用手冊》第11.2節所描述的“擴展I/O中斷”；
/linux/arch/loongarch/include/asm/
H A Dkvm_pch_pic.h53 uint8_t route_entry[64]; /* default value 0, route to int0: eiointc */
54 uint8_t htmsi_vector[64]; /* irq route table for routing to eiointc */
/linux/drivers/irqchip/
H A Dirq-loongson-eiointc.c8 #define pr_fmt(fmt) "eiointc: " fmt
290 .name = "EIOINTC",
471 "irqchip/loongarch/eiointc:starting", in eiointc_init()
551 if (of_device_is_compatible(of_node, "loongson,ls2k0500-eiointc")) in eiointc_of_init()
570 IRQCHIP_DECLARE(loongson_ls2k0500_eiointc, "loongson,ls2k0500-eiointc", eiointc_of_init);
571 IRQCHIP_DECLARE(loongson_ls2k2000_eiointc, "loongson,ls2k2000-eiointc", eiointc_of_init);
H A DMakefile123 obj-$(CONFIG_LOONGSON_EIOINTC) += irq-loongson-eiointc.o
/linux/arch/loongarch/kvm/
H A Dmain.c404 /* Register LoongArch EIOINTC interrupt controller interface. */ in kvm_loongarch_env_init()