| /linux/drivers/phy/mediatek/ |
| H A D | phy-mtk-dp.c | 87 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_init() local
97 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE0_DRIVING_PARAM_3, in mtk_dp_phy_init()
99 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE1_DRIVING_PARAM_3, in mtk_dp_phy_init()
101 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE2_DRIVING_PARAM_3, in mtk_dp_phy_init()
103 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE3_DRIVING_PARAM_3, in mtk_dp_phy_init()
111 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_configure() local
134 regmap_write(dp_phy->regs, MTK_DP_PHY_DIG_BIT_RATE, val); in mtk_dp_phy_configure()
137 regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1, in mtk_dp_phy_configure()
145 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_reset() local
147 regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, in mtk_dp_phy_reset()
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| /linux/drivers/gpu/drm/msm/dp/ |
| H A D | dp_ctrl.c | 1311 enum drm_dp_phy dp_phy) in msm_dp_ctrl_update_phy_vx_px() argument
1354 if (dp_phy == DP_PHY_DPRX) in msm_dp_ctrl_update_phy_vx_px()
1357 reg = DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy); in msm_dp_ctrl_update_phy_vx_px()
1367 u8 pattern, enum drm_dp_phy dp_phy) in msm_dp_ctrl_train_pattern_set() argument
1380 if (dp_phy == DP_PHY_DPRX) in msm_dp_ctrl_train_pattern_set()
1383 reg = DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy); in msm_dp_ctrl_train_pattern_set()
1414 int *training_step, enum drm_dp_phy dp_phy) in msm_dp_ctrl_link_train_1() argument
1422 ctrl->panel->dpcd, dp_phy, false); in msm_dp_ctrl_link_train_1()
1432 DP_LINK_SCRAMBLING_DISABLE, dp_phy); in msm_dp_ctrl_link_train_1()
1435 ret = msm_dp_ctrl_update_phy_vx_px(ctrl, dp_phy); in msm_dp_ctrl_link_train_1()
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| /linux/include/drm/display/ |
| H A D | drm_dp.h | 1530 #define DP_LTTPR_BASE(dp_phy) \ argument
1532 ((dp_phy) - DP_PHY_LTTPR1))
1534 #define DP_LTTPR_REG(dp_phy, lttpr1_reg) \ argument
1535 (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))
1538 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \ argument
1539 DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1)
1542 #define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \ argument
1543 DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1)
1549 #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \ argument
1550 DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
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| H A D | drm_dp_helper.h | 48 enum drm_dp_phy dp_phy, bool uhbr);
50 enum drm_dp_phy dp_phy, bool uhbr);
72 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy);
666 enum drm_dp_phy dp_phy,
730 enum drm_dp_phy dp_phy,
770 int drm_dp_dump_lttpr_desc(struct drm_dp_aux *aux, enum drm_dp_phy dp_phy);
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| /linux/Documentation/devicetree/bindings/display/msm/ |
| H A D | dp-controller.yaml | 213 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
215 phys = <&dp_phy>;
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| H A D | qcom,sm7150-mdss.yaml | 404 assigned-clock-parents = <&dp_phy 0>,
405 <&dp_phy 1>;
410 phys = <&dp_phy>;
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | qcom,sc7280-dispcc.yaml | 66 <&dp_phy 0>,
67 <&dp_phy 1>,
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| H A D | qcom,sm7150-dispcc.yaml | 68 <&dp_phy 0>,
69 <&dp_phy 1>;
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| H A D | qcom,dispcc-sm6125.yaml | 87 <&dp_phy 0>,
88 <&dp_phy 1>,
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| /linux/drivers/gpu/drm/display/ |
| H A D | drm_dp_helper.c | 288 enum drm_dp_phy dp_phy, bool uhbr, bool cr) in __read_delay() argument
294 if (dp_phy == DP_PHY_DPRX) { in __read_delay()
315 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); in __read_delay()
322 offset = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); in __read_delay()
343 enum drm_dp_phy dp_phy, bool uhbr) in drm_dp_read_clock_recovery_delay() argument
345 return __read_delay(aux, dpcd, dp_phy, uhbr, true); in drm_dp_read_clock_recovery_delay()
350 enum drm_dp_phy dp_phy, bool uhbr) in drm_dp_read_channel_eq_delay() argument
352 return __read_delay(aux, dpcd, dp_phy, uhbr, false); in drm_dp_read_channel_eq_delay()
411 * @dp_phy: The DP PHY identifier
413 * Given the @dp_phy, get a user friendly name of the DP PHY, either "DPRX" or
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| /linux/Documentation/devicetree/bindings/display/rockchip/ |
| H A D | rockchip,analogix-dp.yaml | 89 phys = <&dp_phy>;
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| /linux/Documentation/devicetree/bindings/display/bridge/ |
| H A D | cdns,mhdp8546.yaml | 140 phys = <&dp_phy>;
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| /linux/Documentation/devicetree/bindings/display/samsung/ |
| H A D | samsung,exynos5-dp.yaml | 144 phys = <&dp_phy>;
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| /linux/arch/arm/boot/dts/samsung/ |
| H A D | exynos5250.dtsi | 298 dp_phy: dp-phy { label
1126 phys = <&dp_phy>;
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| H A D | exynos5420.dtsi | 933 dp_phy: dp-phy { label
1213 phys = <&dp_phy>;
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