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/linux/Documentation/driver-api/soundwire/
H A Dbra.rst135 be programmed by setting the DP0 registers as:
176 by a single DP0 data port, and at the low-level the bus ownership can
292 BRA, the DP0 is the destination. DP0 registers are standard and
295 Peripherals on a link and some of them do not support DP0, the
296 write commands to program DP0 registers will generate harmless
298 responses from Peripherals which support DP0. In other words,
299 the DP0 programming can be done with broadcast commands, and
304 machine driver will not create a dailink relying on DP0. The
312 DP0 port
[all...]
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-soundwire-slave48 What: /sys/bus/soundwire/devices/sdw:.../dp0/max_word
49 /sys/bus/soundwire/devices/sdw:.../dp0/min_word
50 /sys/bus/soundwire/devices/sdw:.../dp0/words
51 /sys/bus/soundwire/devices/sdw:.../dp0/BRA_flow_controlled
52 /sys/bus/soundwire/devices/sdw:.../dp0/simple_ch_prep_sm
53 /sys/bus/soundwire/devices/sdw:.../dp0/imp_def_interrupts
/linux/drivers/soundwire/
H A Dsysfs_slave.c43 * |---- dp0
138 * DP0 sysfs
201 DEFINE_SYSFS_GROUP_VISIBLE(dp0);
205 .is_visible = SYSFS_GROUP_VISIBLE(dp0),
206 .name = "dp0",
H A Ddebugfs.c69 /* DP0 non-banked registers */ in sdw_slave_reg_show()
74 /* DP0 Bank 0 registers */ in sdw_slave_reg_show()
80 /* DP0 Bank 1 registers */ in sdw_slave_reg_show()
H A Dbus.c1471 /* No need to continue if DP0 is not present */ in sdw_initialize_slave()
1475 /* Enable DP0 interrupts */ in sdw_initialize_slave()
1537 /* Read DP0 interrupt again */ in sdw_handle_dp0_interrupt()
1553 dev_warn(&slave->dev, "Reached MAX_RETRY on DP0 read\n"); in sdw_handle_dp0_interrupt()
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
H A Dpipeline.json33 "PublicDescription": "Duration for which all slots in the data processing issue queue are busy. This event counts the cycles where all slots in the DP0 and DP1 IQs are full with micro-operations waiting for issuing, and the despatch stage is not empty",
36 "BriefDescription": "Duration for which all slots in the data processing issue queue are busy. This event counts the cycles where all slots in the DP0 and DP1 IQs are full with micro-operations waiting for issuing, and the despatch stage is not empty"
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sa8775p-dispcc.yaml30 - description: Link clock from DP0 PHY
31 - description: VCO DIV clock from DP0 PHY
/linux/drivers/parisc/
H A Diosapic.c517 static void iosapic_rd_irt_entry(struct vector_info *vi , u32 *dp0, u32 *dp1) in iosapic_rd_irt_entry() argument
522 *dp0 = iosapic_read(isp->addr, IOSAPIC_IRDT_ENTRY(idx)); in iosapic_rd_irt_entry()
527 static void iosapic_wr_irt_entry(struct vector_info *vi, u32 dp0, u32 dp1) in iosapic_wr_irt_entry() argument
532 vi->irqline, isp->isi_hpa, dp0, dp1); in iosapic_wr_irt_entry()
534 iosapic_write(isp->addr, IOSAPIC_IRDT_ENTRY(vi->irqline), dp0); in iosapic_wr_irt_entry()
537 dp0 = readl(isp->addr+IOSAPIC_REG_WINDOW); in iosapic_wr_irt_entry()
546 ** set_irt prepares the data (dp0, dp1) according to the vector_info
547 ** and target cpu (id_eid). dp0/dp1 are then used to program I/O SAPIC
551 iosapic_set_irt_data( struct vector_info *vi, u32 *dp0, u32 *dp1) in iosapic_set_irt_data() argument
567 *dp0 in iosapic_set_irt_data()
[all...]
/linux/drivers/gpu/drm/bridge/
H A Dtc358767.c190 #define DP0_VIDMNGEN0 0x0610 /* DP0 Video Force M Value Register */
191 #define DP0_VIDMNGEN1 0x0614 /* DP0 Video Force N Value Register */
192 #define DP0_VMNGENSTATUS 0x0618 /* DP0 Video Current M Value Register */
193 #define DP0_AUDMNGEN0 0x0628 /* DP0 Audio Force M Value Register */
194 #define DP0_AUDMNGEN1 0x062c /* DP0 Audio Force N Value Register */
195 #define DP0_AMNGENSTATUS 0x0630 /* DP0 Audio Current M Value Register */
269 #define DP0_TPATDAT0 0x06e8 /* DP0 Test Pattern bits 29 to 0 */
270 #define DP0_TPATDAT1 0x06ec /* DP0 Test Pattern bits 59 to 30 */
271 #define DP0_TPATDAT2 0x06f0 /* DP0 Test Pattern bits 89 to 60 */
272 #define DP0_TPATDAT3 0x06f4 /* DP0 Tes
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/linux/drivers/usb/typec/mux/
H A Dptn36502.c135 * D -> DP0 in ptn36502_set()
137 * A -> DP0 in ptn36502_set()
157 * D -> DP0 in ptn36502_set()
159 * A -> DP0 in ptn36502_set()
H A Dnb7vpq904m.c186 * D -> DP0 in nb7vpq904m_set()
188 * A -> DP0 in nb7vpq904m_set()
225 * D -> DP0 in nb7vpq904m_set()
227 * A -> DP0 in nb7vpq904m_set()
/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml108 hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib,
118 hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
/linux/Documentation/devicetree/bindings/display/connector/
H A Ddp-connector.yaml45 label = "dp0";
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4-j742s2-evm-common.dtsi230 dp0_pwr_3v3: regulator-dp0-prw {
232 regulator-name = "dp0-pwr";
239 dp0: connector-dp0 { label
241 label = "DP0";
379 dp0_pins_default: dp0-default-pins {
H A Dk3-j721e-beagleboneai64.dts293 dp0: connector { label
295 label = "DP0";
362 dp0_3v3_en_pins_default:dp0-3v3-en-default-pins {
368 dp0_pins_default: dp0-default-pins {
H A Dk3-j721e-sk.dts286 dp0: connector { label
288 label = "DP0";
475 dp0_pins_default: dp0-default-pins {
/linux/Documentation/devicetree/bindings/display/
H A Darm,malidp.yaml102 dp0: malidp@6f200000 {
/linux/arch/arm64/boot/dts/arm/
H A Dmorello-sdp.dts59 dp0: display@2cc00000 { label
/linux/sound/soc/codecs/
H A Dsdw-mockup.c147 * DP0 is not supported in sdw_mockup_read_prop()
/linux/sound/soc/qcom/
H A Dcommon.c16 SND_SOC_DAPM_SPK("DP0 Jack", NULL),
/linux/sound/hda/codecs/hdmi/
H A Dtegrahdmi.c297 HDA_CODEC_ID_MODEL(0x10de002d, "Tegra186 HDMI/DP0", MODEL_TEGRA),
/linux/arch/arm64/boot/dts/qcom/
H A Dsa8775p-ride.dtsi166 dp0-connector {
951 dp0_hot_plug_det: dp0-hot-plug-det-state {
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dnpc.h260 u16 dp0; member
/linux/include/linux/soundwire/
H A Dsdw.h242 * struct sdw_dp0_prop - DP0 properties
256 * @lane_list: indicates which Lanes can be used by DP0
/linux/drivers/soc/tegra/
H A Dpmc.c3756 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),
3797 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
3964 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),
4016 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
4127 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, UINT_MAX, "hdmi-dp0"),
4145 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),

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