| /linux-5.10/Documentation/devicetree/bindings/dma/ |
| D | lpc1850-dmamux.txt | 1 NXP LPC18xx/43xx DMA MUX (DMA request router)
4 - compatible: "nxp,lpc1850-dmamux"
5 - reg: Memory map for accessing module
6 - #dma-cells: Should be set to <3>.
7 * 1st cell contain the master dma request signal
8 * 2nd cell contain the mux value (0-3) for the peripheral
11 - dma-requests: Number of DMA requests for the mux
12 - dma-masters: phandle pointing to the DMA controller
14 The DMA controller node need to have the following poroperties:
15 - dma-requests: Number of DMA requests the controller can handle
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| D | ti-dma-crossbar.txt | 1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
5 "ti,am335x-edma-crossbar" for AM335x and AM437x
6 - reg: Memory map for accessing module
7 - #dma-cells: Should be set to to match with the DMA controller's dma-cells
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
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| D | fsl-imx-dma.txt | 1 * Freescale Direct Memory Access (DMA) Controller for i.MX
3 This document will only describe differences to the generic DMA Controller and
4 DMA request bindings as described in dma/dma.txt .
6 * DMA controller
9 - compatible : Should be "fsl,<chip>-dma". chip can be imx1, imx21 or imx27
10 - reg : Should contain DMA registers location and length
11 - interrupts : First item should be DMA interrupt, second one is optional and
12 should contain DMA Error interrupt
13 - #dma-cells : Has to be 1. imx-dma does not support anything else.
16 - #dma-channels : Number of DMA channels supported. Should be 16.
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| D | mtk-uart-apdma.txt | 4 - compatible should contain:
5 * "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA
6 * "mediatek,mt6577-uart-dma" for MT6577 and all of the above
8 - reg: The base address of the APDMA register bank.
10 - interrupts: A single interrupt specifier.
11 One interrupt per dma-requests, or 8 if no dma-requests property is present
13 - dma-requests: The number of DMA channels
15 - clocks : Must contain an entry for each entry in clock-names.
16 See ../clocks/clock-bindings.txt for details.
17 - clock-names: The APDMA clock for register accesses
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| D | dma-router.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/dma-router.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DMA Router Generic Binding
10 - Vinod Koul <vkoul@kernel.org>
13 - $ref: "dma-common.yaml#"
16 DMA routers are transparent IP blocks used to route DMA request
17 lines from devices to the DMA controller. Some SoCs (like TI DRA7x)
18 have more peripherals integrated with DMA requests than what the DMA
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| D | owl-dma.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/owl-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Actions Semi Owl SoCs DMA controller
10 The OWL DMA is a general-purpose direct memory access controller capable of
11 supporting 10 and 12 independent DMA channels for S700 and S900 SoCs
15 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 - $ref: "dma-controller.yaml#"
23 - actions,s900-dma
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| D | arm-pl330.txt | 1 * ARM PrimeCell PL330 DMA Controller
3 The ARM PrimeCell PL330 DMA controller can move blocks of memory contents
7 - compatible: should include both "arm,pl330" and "arm,primecell".
8 - reg: physical base address of the controller and length of memory mapped
10 - interrupts: interrupt number to the cpu.
13 - dma-coherent : Present if dma operations are coherent
14 - #dma-cells: must be <1>. used to represent the number of integer
16 - dma-channels: contains the total number of DMA channels supported by the DMAC
17 - dma-requests: contains the total number of DMA requests supported by the DMAC
18 - arm,pl330-broken-no-flushp: quirk for avoiding to execute DMAFLUSHP
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| D | zxdma.txt | 1 * ZTE ZX296702 DMA controller
4 - compatible: Should be "zte,zx296702-dma"
5 - reg: Should contain DMA registers location and length.
6 - interrupts: Should contain one interrupt shared by all channel
7 - #dma-cells: see dma.txt, should be 1, para number
8 - dma-channels: physical channels supported
9 - dma-requests: virtual channels supported, each virtual channel
11 - clocks: clock required
16 dma: dma-controller@09c00000{
17 compatible = "zte,zx296702-dma";
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| D | k3dma.txt | 1 * Hisilicon K3 DMA controller
3 See dma.txt first
6 - compatible: Must be one of
7 - "hisilicon,k3-dma-1.0"
8 - "hisilicon,hisi-pcm-asp-dma-1.0"
9 - reg: Should contain DMA registers location and length.
10 - interrupts: Should contain one interrupt shared by all channel
11 - #dma-cells: see dma.txt, should be 1, para number
12 - dma-channels: physical channels supported
13 - dma-requests: virtual channels supported, each virtual channel
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| D | renesas,nbpfaxi.txt | 1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
3 * DMA controller
7 - compatible: must be one of
17 - #dma-cells: must be 2: the first integer is a terminal number, to which this
26 - max-burst-mem-read: limit burst size for memory reads
29 - max-burst-mem-write: limit burst size for memory writes
32 If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM
35 You can use dma-channels and dma-requests as described in dma.txt, although they
40 dma: dma-controller@48000000 {
51 #dma-cells = <2>;
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| D | renesas,shdma.txt | 3 Sh-/r-mobile and R-Car systems often have multiple identical DMA controller
4 instances, capable of serving any of a common set of DMA slave devices, using
6 SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible
7 DMAC instances have the same number of channels and use the same DMA
8 descriptors. Therefore respective DMA DT bindings can also all be placed in the
12 * DMA multiplexer
15 - compatible: should be "renesas,shdma-mux"
16 - #dma-cells: should be <1>, see "dmas" property below
19 - dma-channels: number of DMA channels
20 - dma-requests: number of DMA request signals
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| D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DMA Controller bindings
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
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| D | arm-pl08x.txt | 1 * ARM PrimeCells PL080 and PL081 and derivatives DMA controller
4 - compatible: "arm,pl080", "arm,primecell";
7 - arm,primecell-periphid: on the FTDMAC020 the primecell ID is not hard-coded
11 - reg: Address range of the PL08x registers
12 - interrupt: The PL08x interrupt number
13 - clocks: The clock running the IP core clock
14 - clock-names: Must contain "apb_pclk"
15 - lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
16 - lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs
17 - mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
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| D | st_fdma.txt | 3 The FDMA is a general-purpose direct memory access controller capable of
4 supporting 16 independent DMA channels. It accepts up to 32 DMA requests.
10 - compatible : Should be one of
11 - st,stih407-fdma-mpe31-11, "st,slim-rproc";
12 - st,stih407-fdma-mpe31-12, "st,slim-rproc";
13 - st,stih407-fdma-mpe31-13, "st,slim-rproc";
14 - reg : Should contain an entry for each name in reg-names
15 - reg-names : Must contain "slimcore", "dmem", "peripherals", "imem" entries
16 - interrupts : Should contain one interrupt shared by all channels
17 - dma-channels : Number of channels supported by the controller
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| D | st,stm32-mdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
11 supporting 64 independent DMA channels with 256 HW requests.
12 DMA clients connected to the STM32 MDMA controller must use the format
13 described in the dma.txt file, using a five-cell specifier for each channel:
21 3. A 32bit mask specifying the DMA channel configuration
22 -bit 0-1: Source increment mode
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| /linux-5.10/Documentation/vm/ |
| D | balance.rst | 15 overhead of page reclaim. This may happen for opportunistic high-order
16 allocation requests that have order-0 fallback options. In such cases,
19 __GFP_IO allocation requests are made to prevent file system deadlocks.
21 In the absence of non sleepable allocation requests, it seems detrimental
26 That being said, the kernel should try to fulfill requests for direct
28 the dma pool, so as to keep the dma pool filled for dma requests (atomic
30 OTOH, if there is a lot of free dma pages, it is preferable to satisfy
31 regular memory requests by allocating one from the dma pool, instead
36 right ratio of dma and regular memory, it is quite possible that balancing
37 would not be done even when the dma zone was completely empty. 2.2 has
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| /linux-5.10/drivers/dma/ |
| D | stm32-dmamux.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
8 * DMA Router driver for STM32 DMA MUX
10 * Based on TI DMA Crossbar driver
39 u32 dma_requests; /* Number of DMA requests connected to DMAMUX */
40 u32 dmamux_requests; /* Number of DMA requests routed toward DMAs */
42 unsigned long *dma_inuse; /* Used DMA channel */
46 u32 dma_reqs[]; /* Number of DMA Request per DMA masters.
47 * [0] holds number of DMA Masters.
68 /* Clear dma request */ in stm32_dmamux_free()
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| D | lpc18xx-dmamux.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * DMA Router driver for LPC18xx/43xx DMA MUX
7 * Based on TI DMA Crossbar driver by:
8 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
46 spin_lock_irqsave(&dmamux->lock, flags); in lpc18xx_dmamux_free()
47 mux->busy = false; in lpc18xx_dmamux_free()
48 spin_unlock_irqrestore(&dmamux->lock, flags); in lpc18xx_dmamux_free()
54 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); in lpc18xx_dmamux_reserve()
59 if (dma_spec->args_count != 3) { in lpc18xx_dmamux_reserve()
60 dev_err(&pdev->dev, "invalid number of dma mux args\n"); in lpc18xx_dmamux_reserve()
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| /linux-5.10/drivers/dma/ti/ |
| D | dma-crossbar.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
24 .compatible = "ti,dra7-dma-crossbar",
28 .compatible = "ti,am335x-edma-crossbar",
43 u32 dma_requests; /* number of DMA requests on eDMA */
59 writeb_relaxed(val, iomem + (63 - event % 4)); in ti_am335x_xbar_write()
70 map->mux_val, map->dma_line); in ti_am335x_xbar_free()
72 ti_am335x_xbar_write(xbar->iomem, map->dma_line, 0); in ti_am335x_xbar_free()
79 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); in ti_am335x_xbar_route_allocate()
83 if (dma_spec->args_count != 3) in ti_am335x_xbar_route_allocate()
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| /linux-5.10/Documentation/driver-api/rapidio/ |
| D | mport_cdev.rst | 17 for user-space applications. Most of RapidIO operations are supported through
24 Using available set of ioctl commands user-space applications can perform
27 - Reads and writes from/to configuration registers of mport devices
29 - Reads and writes from/to configuration registers of remote RapidIO devices.
32 - Set RapidIO Destination ID for mport devices (RIO_MPORT_MAINT_HDID_SET)
33 - Set RapidIO Component Tag for mport devices (RIO_MPORT_MAINT_COMPTAG_SET)
34 - Query logical index of mport devices (RIO_MPORT_MAINT_PORT_IDX_GET)
35 - Query capabilities and RapidIO link configuration of mport devices
37 - Enable/Disable reporting of RapidIO doorbell events to user-space applications
39 - Enable/Disable reporting of RIO port-write events to user-space applications
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| /linux-5.10/Documentation/devicetree/bindings/net/ |
| D | snps,dwc-qos-ethernet.txt | 13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
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| /linux-5.10/Documentation/core-api/ |
| D | debugging-via-ohci1394.rst | 2 Using physical DMA provided by OHCI-1394 FireWire controllers for debugging
6 ------------
9 to the OHCI-1394 specification which defines the controller to be a PCI
10 bus master which uses DMA to offload data transfers from the CPU and has
11 a "Physical Response Unit" which executes specific requests by employing
12 PCI-Bus master DMA after applying filters defined by the OHCI-1394 driver.
14 Once properly configured, remote machines can send these requests to
15 ask the OHCI-1394 controller to perform read and write requests on
16 physical system memory and, for read requests, send the result of
28 more common hardware such as x86, x86-64 and PowerPC.
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| /linux-5.10/Documentation/driver-api/mmc/ |
| D | mmc-async-req.rst | 11 pre-fetch makes the cache overhead relatively significant. If the DMA
13 transfer, the DMA preparation overhead would not affect the MMC performance.
15 The intention of non-blocking (asynchronous) MMC requests is to minimize the
19 dma_unmap_sg are processing. Using non-blocking MMC requests makes it
26 The mmc_blk_issue_rw_rq() in the MMC block driver is made non-blocking.
33 platform. In power save mode, when clocks run on a lower frequency, the DMA
40 https://wiki.linaro.org/WorkingGroups/Kernel/Specs/StoragePerfMMC-async-req
48 truly non-blocking. If there is an ongoing async request it waits
56 There are two optional members in the mmc_host_ops -- pre_req() and
57 post_req() -- that the host driver may implement in order to move work
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| /linux-5.10/arch/arm/mach-ep93xx/ |
| D | dma.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/mach-ep93xx/dma.c
9 * This work is based on the original dma-m2p implementation with
18 #include <linux/dma-mapping.h>
24 #include <linux/platform_data/dma-ep93xx.h>
33 * DMA M2P channels.
38 * I2S contains 3 Tx and 3 Rx DMA Channels
39 * AAC contains 3 Tx and 3 Rx DMA Channels
40 * UART1 contains 1 Tx and 1 Rx DMA Channels
41 * UART2 contains 1 Tx and 1 Rx DMA Channels
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| /linux-5.10/Documentation/ide/ |
| D | ChangeLog.ide-tape.1995-2002 | 2 * Ver 0.1 Nov 1 95 Pre-working code :-)
8 * we received non serial read-ahead requests from the
17 * ide tapes :-)
34 * requests are relatively fast, and once we are
35 * performing one tape r/w request, a lot of requests
50 * postponed and ide.c is free to handle requests from
73 * Removed some old (non-active) code which had
75 * requests.
96 * Pre-calculation of the expected read/write request
109 * continuous view of the media - any mix of block sizes
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