Home
last modified time | relevance | path

Searched full:display (Results 1 – 25 of 3131) sorted by relevance

12345678910>>...126

/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_irq.c36 intel_display_irq_regs_init(struct intel_display *display, struct i915_irq_regs regs, in intel_display_irq_regs_init() argument
39 intel_dmc_wl_get(display, regs.imr); in intel_display_irq_regs_init()
40 intel_dmc_wl_get(display, regs.ier); in intel_display_irq_regs_init()
41 intel_dmc_wl_get(display, regs.iir); in intel_display_irq_regs_init()
43 gen2_irq_init(to_intel_uncore(display->drm), regs, imr_val, ier_val); in intel_display_irq_regs_init()
45 intel_dmc_wl_put(display, regs.iir); in intel_display_irq_regs_init()
46 intel_dmc_wl_put(display, regs.ier); in intel_display_irq_regs_init()
47 intel_dmc_wl_put(display, regs.imr); in intel_display_irq_regs_init()
51 intel_display_irq_regs_reset(struct intel_display *display, struct i915_irq_regs regs) in intel_display_irq_regs_reset() argument
53 intel_dmc_wl_get(display, regs.imr); in intel_display_irq_regs_reset()
[all …]
H A Dintel_display_driver.c5 * High level display driver entry points. This is a layer between top level
6 * driver code and low level display functionality; no low level display code or
12 #include <drm/display/drm_dp_mst_helper.h>
86 void intel_display_driver_init_hw(struct intel_display *display) in intel_display_driver_init_hw() argument
88 if (!HAS_DISPLAY(display)) in intel_display_driver_init_hw()
91 intel_cdclk_read_hw(display); in intel_display_driver_init_hw()
93 intel_display_wa_apply(display); in intel_display_driver_init_hw()
111 static void intel_mode_config_init(struct intel_display *display) in intel_mode_config_init() argument
113 struct drm_mode_config *mode_config = &display->drm->mode_config; in intel_mode_config_init()
115 drm_mode_config_init(display->drm); in intel_mode_config_init()
[all …]
H A Dintel_pch.c43 * Check for platforms where the south display is on the same PCI device or SoC
44 * die as the north display. The PCH (if it even exists) is not involved in
45 * display. Return a fake PCH type for south display handling on these
48 static enum intel_pch intel_pch_fake_for_south_display(struct intel_display *display) in intel_pch_fake_for_south_display() argument
52 if (DISPLAY_VER(display) >= 20) in intel_pch_fake_for_south_display()
54 else if (display->platform.battlemage || display->platform.meteorlake) in intel_pch_fake_for_south_display()
56 else if (display->platform.dg2) in intel_pch_fake_for_south_display()
58 else if (display->platform.dg1) in intel_pch_fake_for_south_display()
66 intel_pch_type(const struct intel_display *display, unsigned short id) in intel_pch_type() argument
70 drm_dbg_kms(display->drm, "Found Ibex Peak PCH\n"); in intel_pch_type()
[all …]
H A Di9xx_display_sr.c15 static void i9xx_display_save_swf(struct intel_display *display) in i9xx_display_save_swf() argument
20 if (DISPLAY_VER(display) == 2 && display->platform.mobile) { in i9xx_display_save_swf()
22 display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); in i9xx_display_save_swf()
23 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
26 display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i)); in i9xx_display_save_swf()
27 } else if (DISPLAY_VER(display) == 2) { in i9xx_display_save_swf()
29 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
30 } else if (HAS_GMCH(display)) { in i9xx_display_save_swf()
32 display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); in i9xx_display_save_swf()
33 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
[all …]
H A Dintel_hotplug_irq.c137 static void intel_hpd_init_pins(struct intel_display *display) in intel_hpd_init_pins() argument
139 struct intel_hotplug *hpd = &display->hotplug; in intel_hpd_init_pins()
141 if (HAS_GMCH(display)) { in intel_hpd_init_pins()
142 if (display->platform.g4x || display->platform.valleyview || in intel_hpd_init_pins()
143 display->platform.cherryview) in intel_hpd_init_pins()
150 if (DISPLAY_VER(display) >= 14) in intel_hpd_init_pins()
152 else if (DISPLAY_VER(display) >= 11) in intel_hpd_init_pins()
154 else if (display->platform.geminilake || display->platform.broxton) in intel_hpd_init_pins()
156 else if (DISPLAY_VER(display) == 9) in intel_hpd_init_pins()
158 else if (DISPLAY_VER(display) >= 8) in intel_hpd_init_pins()
[all …]
H A Dintel_display_power_well.c42 static enum skl_power_gate pw_idx_to_pg(struct intel_display *display, int pw_idx) in pw_idx_to_pg() argument
44 int pw1_idx = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_PW_1 : SKL_PW_CTL_IDX_PW_1; in pw_idx_to_pg()
64 void (*sync_hw)(struct intel_display *display,
71 void (*enable)(struct intel_display *display,
77 void (*disable)(struct intel_display *display,
80 bool (*is_enabled)(struct intel_display *display,
91 lookup_power_well(struct intel_display *display, in lookup_power_well() argument
96 for_each_power_well(display, power_well) in lookup_power_well()
103 * to abort things like display initialization sequences. Just return in lookup_power_well()
107 drm_WARN(display->drm, 1, in lookup_power_well()
[all …]
H A Dintel_fdi.c29 static void assert_fdi_tx(struct intel_display *display, in assert_fdi_tx() argument
34 if (HAS_DDI(display)) { in assert_fdi_tx()
42 cur_state = intel_de_read(display, in assert_fdi_tx()
43 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE; in assert_fdi_tx()
45 cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE; in assert_fdi_tx()
47 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, in assert_fdi_tx()
52 void assert_fdi_tx_enabled(struct intel_display *display, enum pipe pipe) in assert_fdi_tx_enabled() argument
54 assert_fdi_tx(display, pipe, true); in assert_fdi_tx_enabled()
57 void assert_fdi_tx_disabled(struct intel_display *display, enum pipe pipe) in assert_fdi_tx_disabled() argument
59 assert_fdi_tx(display, pipe, false); in assert_fdi_tx_disabled()
[all …]
H A Dintel_pch_display.c25 bool intel_has_pch_trancoder(struct intel_display *display, in intel_has_pch_trancoder() argument
28 return HAS_PCH_IBX(display) || HAS_PCH_CPT(display) || in intel_has_pch_trancoder()
29 (HAS_PCH_LPT_H(display) && pch_transcoder == PIPE_A); in intel_has_pch_trancoder()
34 struct intel_display *display = to_intel_display(crtc); in intel_crtc_pch_transcoder() local
36 if (HAS_PCH_LPT(display)) in intel_crtc_pch_transcoder()
42 static void assert_pch_dp_disabled(struct intel_display *display, in assert_pch_dp_disabled() argument
49 state = g4x_dp_port_enabled(display, dp_reg, port, &port_pipe); in assert_pch_dp_disabled()
51 INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe, in assert_pch_dp_disabled()
55 INTEL_DISPLAY_STATE_WARN(display, in assert_pch_dp_disabled()
56 HAS_PCH_IBX(display) && !state && port_pipe == PIPE_B, in assert_pch_dp_disabled()
[all …]
H A Dintel_gmbus.c34 #include <drm/display/drm_hdcp_helper.h>
52 struct intel_display *display; member
153 static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display, in get_gmbus_pin() argument
159 if (INTEL_PCH_TYPE(display) >= PCH_MTL) { in get_gmbus_pin()
162 } else if (INTEL_PCH_TYPE(display) >= PCH_DG2) { in get_gmbus_pin()
165 } else if (INTEL_PCH_TYPE(display) >= PCH_DG1) { in get_gmbus_pin()
168 } else if (INTEL_PCH_TYPE(display) >= PCH_ICP) { in get_gmbus_pin()
171 } else if (HAS_PCH_CNP(display)) { in get_gmbus_pin()
174 } else if (display->platform.geminilake || display->platform.broxton) { in get_gmbus_pin()
177 } else if (DISPLAY_VER(display) == 9) { in get_gmbus_pin()
[all …]
H A Dintel_dmc.c48 * From gen9 onwards we have newly added DMC (Display microcontroller) in display
49 * engine to save and restore the state of display engine when it enter into
65 struct intel_display *display; member
87 static struct intel_dmc *display_to_dmc(struct intel_display *display) in display_to_dmc() argument
89 return display->dmc.dmc; in display_to_dmc()
92 static const char *dmc_firmware_param(struct intel_display *display) in dmc_firmware_param() argument
94 const char *p = display->params.dmc_firmware_path; in dmc_firmware_param()
99 static bool dmc_firmware_param_disabled(struct intel_display *display) in dmc_firmware_param_disabled() argument
101 const char *p = dmc_firmware_param(display); in dmc_firmware_param_disabled()
182 static const char *dmc_firmware_default(struct intel_display *display, u32 *size) in dmc_firmware_default() argument
[all …]
H A Dintel_cdclk.c56 * The display engine uses several different clocks to do its work. There
59 * are the core display clock (CDCLK) and RAWCLK.
61 * CDCLK clocks most of the display pipe logic, and thus its frequency
67 * to minimize power consumption for a given display configuration.
68 * Typically changes to the CDCLK frequency require all the display pipes
154 void (*get_cdclk)(struct intel_display *display,
156 void (*set_cdclk)(struct intel_display *display,
163 void intel_cdclk_get_cdclk(struct intel_display *display, in intel_cdclk_get_cdclk() argument
166 display->funcs.cdclk->get_cdclk(display, cdclk_config); in intel_cdclk_get_cdclk()
169 static void intel_cdclk_set_cdclk(struct intel_display *display, in intel_cdclk_set_cdclk() argument
[all …]
H A Dintel_de.h15 static inline struct intel_uncore *__to_uncore(struct intel_display *display) in __to_uncore() argument
17 return to_intel_uncore(display->drm); in __to_uncore()
21 intel_de_read(struct intel_display *display, i915_reg_t reg) in intel_de_read() argument
25 intel_dmc_wl_get(display, reg); in intel_de_read()
27 val = intel_uncore_read(__to_uncore(display), reg); in intel_de_read()
29 intel_dmc_wl_put(display, reg); in intel_de_read()
35 intel_de_read8(struct intel_display *display, i915_reg_t reg) in intel_de_read8() argument
39 intel_dmc_wl_get(display, reg); in intel_de_read8()
41 val = intel_uncore_read8(__to_uncore(display), reg); in intel_de_read8()
43 intel_dmc_wl_put(display, reg); in intel_de_read8()
[all …]
H A Di9xx_plane.c116 static bool i9xx_plane_has_fbc(struct intel_display *display, in i9xx_plane_has_fbc() argument
119 if (!HAS_FBC(display)) in i9xx_plane_has_fbc()
122 if (display->platform.broadwell || display->platform.haswell) in i9xx_plane_has_fbc()
124 else if (display->platform.ivybridge) in i9xx_plane_has_fbc()
127 else if (DISPLAY_VER(display) >= 4) in i9xx_plane_has_fbc()
133 static struct intel_fbc *i9xx_plane_fbc(struct intel_display *display, in i9xx_plane_fbc() argument
136 if (i9xx_plane_has_fbc(display, i9xx_plane)) in i9xx_plane_fbc()
137 return display->fbc[INTEL_FBC_A]; in i9xx_plane_fbc()
144 struct intel_display *display = to_intel_display(plane); in i9xx_plane_has_windowing() local
147 if (display->platform.cherryview) in i9xx_plane_has_windowing()
[all …]
H A Dvlv_dsi.c91 struct intel_display *display = to_intel_display(&intel_dsi->base); in vlv_dsi_wait_for_fifo_empty() local
97 if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port), in vlv_dsi_wait_for_fifo_empty()
99 drm_err(display->drm, "DPI FIFOs are not empty\n"); in vlv_dsi_wait_for_fifo_empty()
102 static void write_data(struct intel_display *display, in write_data() argument
114 intel_de_write(display, reg, val); in write_data()
118 static void read_data(struct intel_display *display, in read_data() argument
125 u32 val = intel_de_read(display, reg); in read_data()
137 struct intel_display *display = to_intel_display(&intel_dsi->base); in intel_dsi_host_transfer() local
152 data_reg = MIPI_LP_GEN_DATA(display, port); in intel_dsi_host_transfer()
154 ctrl_reg = MIPI_LP_GEN_CTRL(display, port); in intel_dsi_host_transfer()
[all …]
H A Dintel_combo_phy.c58 icl_get_procmon_ref_values(struct intel_display *display, enum phy phy) in icl_get_procmon_ref_values() argument
62 val = intel_de_read(display, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
80 static void icl_set_procmon_ref_values(struct intel_display *display, in icl_set_procmon_ref_values() argument
85 procmon = icl_get_procmon_ref_values(display, phy); in icl_set_procmon_ref_values()
87 intel_de_rmw(display, ICL_PORT_COMP_DW1(phy), in icl_set_procmon_ref_values()
90 intel_de_write(display, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
91 intel_de_write(display, ICL_PORT_COMP_DW10(phy), procmon->dw10); in icl_set_procmon_ref_values()
94 static bool check_phy_reg(struct intel_display *display, in check_phy_reg() argument
98 u32 val = intel_de_read(display, reg); in check_phy_reg()
101 drm_dbg_kms(display->drm, in check_phy_reg()
[all …]
H A Dintel_wm.c19 * @display: display device
50 void intel_update_watermarks(struct intel_display *display) in intel_update_watermarks() argument
52 if (display->funcs.wm->update_wm) in intel_update_watermarks()
53 display->funcs.wm->update_wm(display); in intel_update_watermarks()
59 struct intel_display *display = to_intel_display(state); in intel_wm_compute() local
61 if (!display->funcs.wm->compute_watermarks) in intel_wm_compute()
64 return display->funcs.wm->compute_watermarks(state, crtc); in intel_wm_compute()
70 struct intel_display *display = to_intel_display(state); in intel_initial_watermarks() local
72 if (display->funcs.wm->initial_watermarks) { in intel_initial_watermarks()
73 display->funcs.wm->initial_watermarks(state, crtc); in intel_initial_watermarks()
[all …]
H A Dintel_flipq.c98 struct intel_display *display = to_intel_display(crtc); in intel_flipq_crtc_init() local
107 drm_dbg_kms(display->drm, "[CRTC:%d:%s] FQ %d: start 0x%x\n", in intel_flipq_crtc_init()
113 bool intel_flipq_supported(struct intel_display *display) in intel_flipq_supported() argument
115 if (!display->params.enable_flipq) in intel_flipq_supported()
118 if (!display->dmc.dmc) in intel_flipq_supported()
121 if (DISPLAY_VER(display) == 20) in intel_flipq_supported()
125 return DISPLAY_VER(display) >= 30 && intel_vrr_always_use_vrr_tg(display); in intel_flipq_supported()
128 void intel_flipq_init(struct intel_display *display) in intel_flipq_init() argument
132 intel_dmc_wait_fw_load(display); in intel_flipq_init()
134 for_each_intel_crtc(display->drm, crtc) in intel_flipq_init()
[all …]
H A Dintel_display_irq.h19 void valleyview_enable_display_irqs(struct intel_display *display);
20 void valleyview_disable_display_irqs(struct intel_display *display);
22 void ilk_update_display_irq(struct intel_display *display,
24 void ilk_enable_display_irq(struct intel_display *display, u32 bits);
25 void ilk_disable_display_irq(struct intel_display *display, u32 bits);
27 void bdw_update_port_irq(struct intel_display *display, u32 interrupt_mask, u32 enabled_irq_mask);
28 void bdw_enable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits);
29 void bdw_disable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits);
31 void ibx_display_interrupt_update(struct intel_display *display,
33 void ibx_enable_display_interrupt(struct intel_display *display, u32 bits);
[all …]
H A Dintel_vrr.c21 struct intel_display *display = to_intel_display(connector); in intel_vrr_is_capable() local
49 return HAS_VRR(display) && in intel_vrr_is_capable()
88 static int intel_vrr_extra_vblank_delay(struct intel_display *display) in intel_vrr_extra_vblank_delay() argument
98 return DISPLAY_VER(display) < 13 ? 1 : 0; in intel_vrr_extra_vblank_delay()
103 struct intel_display *display = to_intel_display(crtc_state); in intel_vrr_vblank_delay() local
106 intel_vrr_extra_vblank_delay(display); in intel_vrr_vblank_delay()
109 static int intel_vrr_flipline_offset(struct intel_display *display) in intel_vrr_flipline_offset() argument
112 return DISPLAY_VER(display) < 13 ? 1 : 0; in intel_vrr_flipline_offset()
117 struct intel_display *display = to_intel_display(crtc_state); in intel_vrr_vmin_flipline() local
119 return crtc_state->vrr.vmin + intel_vrr_flipline_offset(display); in intel_vrr_vmin_flipline()
[all …]
H A Dintel_audio.c43 * DOC: High Definition Audio over HDMI and Display Port
46 * HDMI and Display Port. The audio programming sequences are divided into audio
191 static bool needs_wa_14020863754(struct intel_display *display) in needs_wa_14020863754() argument
193 return DISPLAY_VERx100(display) == 3000 || in needs_wa_14020863754()
194 DISPLAY_VERx100(display) == 2000 || in needs_wa_14020863754()
195 DISPLAY_VERx100(display) == 1401; in needs_wa_14020863754()
201 struct intel_display *display = to_intel_display(crtc_state); in audio_config_hdmi_pixel_clock() local
211 if (DISPLAY_VER(display) < 12 && adjusted_mode->crtc_clock > 148500) in audio_config_hdmi_pixel_clock()
215 drm_dbg_kms(display->drm, in audio_config_hdmi_pixel_clock()
221 drm_dbg_kms(display->drm, in audio_config_hdmi_pixel_clock()
[all …]
H A Dintel_pps.c26 static void vlv_steal_power_sequencer(struct intel_display *display,
34 struct intel_display *display = to_intel_display(intel_dp); in pps_name() local
37 if (display->platform.valleyview || display->platform.cherryview) { in pps_name()
70 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_lock() local
76 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); in intel_pps_lock()
77 mutex_lock(&display->pps.mutex); in intel_pps_lock()
85 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_unlock() local
87 mutex_unlock(&display->pps.mutex); in intel_pps_unlock()
88 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); in intel_pps_unlock()
96 struct intel_display *display = to_intel_display(intel_dp); in vlv_power_sequencer_kick() local
[all …]
/linux/drivers/gpu/drm/i915/
H A DMakefile12 # Support compiling the display code separately for both i915 and xe
220 display/hsw_ips.o \
221 display/i9xx_display_sr.o \
222 display/i9xx_plane.o \
223 display/i9xx_wm.o \
224 display/intel_alpm.o \
225 display/intel_atomic.o \
226 display/intel_audio.o \
227 display/intel_bios.o \
228 display/intel_bo.o \
[all …]
/linux/drivers/gpu/drm/xe/display/
H A Dxe_display.c42 struct intel_display *display = xe->display; in has_display() local
44 return HAS_DISPLAY(display); in has_display()
52 * Note: This is called before xe or display device creation.
65 * xe_display_driver_set_hooks - Add driver flags and hooks for display
69 * display IP. This sets the driver's capability of driving display, regardless
72 * Note: This is called before xe or display device creation.
94 struct intel_display *display = xe->display; in xe_display_fini_early() local
99 intel_display_driver_remove_nogem(display); in xe_display_fini_early()
100 intel_display_driver_remove_noirq(display); in xe_display_fini_early()
101 intel_opregion_cleanup(display); in xe_display_fini_early()
[all …]
/linux/drivers/gpu/drm/xe/
H A DMakefile174 # i915 Display compat #defines and #includes
176 -I$(src)/display/ext \
178 -I$(srctree)/drivers/gpu/drm/i915/display/ \
186 # Rule to build display code shared with i915
187 $(obj)/i915-display/%.o: $(srctree)/drivers/gpu/drm/i915/display/%.c FORCE
191 # Display code specific to xe
193 display/ext/i915_irq.o \
194 display/ext/i915_utils.o \
195 display/intel_bo.o \
196 display/intel_fb_bo.o \
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dfsl,imx8qxp-dc-intc.yaml7 title: Freescale i.MX8qxp Display Controller interrupt controller
10 The Display Controller has a built-in interrupt controller with the following
50 (display controller, content stream 0)
53 (display controller, content stream 0)
56 (display controller, content stream 0)
59 (display controller, safety stream 0)
62 (display controller, safety stream 0)
65 (display controller, safety stream 0)
68 (display controller, content stream 1)
71 (display controller, content stream 1)
[all …]

12345678910>>...126