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/linux-5.10/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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/linux-5.10/arch/parisc/kernel/
Dcache.c6 * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
10 * Cache and TLB management
44 * by software. We need a spinlock around all TLB flushes to ensure
99 test_bit(PG_dcache_dirty, &page->flags)) { in update_mmu_cache()
101 clear_bit(PG_dcache_dirty, &page->flags); in update_mmu_cache()
111 seq_printf(m, "I-cache\t\t: %ld KB\n", in show_cache_info()
114 snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop); in show_cache_info()
115 seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n", in show_cache_info()
118 (cache_info.dc_conf.cc_sh ? ", shared I/D":""), in show_cache_info()
123 cache_info.dt_conf.tc_sh ? " - shared with ITLB":"" in show_cache_info()
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/linux-5.10/Documentation/devicetree/bindings/riscv/
Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
28 - items:
29 - enum:
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/linux-5.10/arch/arc/mm/
Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TLB Management (flush/create/diagnostics) for ARC700
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
11 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
13 * = page-fault thrice as fast (75 usec to 28 usec)
18 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
22 * -MMU v2/v3 BCRs decoded differently
23 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
24 * -tlb_entry_erase( ) can be void
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Dtlbex.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * TLB Exception Handling for ARC
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -MMU v1: moved out legacy code into a seperate file
9 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
13 * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
14 * entry, so that it doesn't knock out it's I-TLB entry
15 * -Some more fine tuning:
19 * -Practically rewrote the I/D TLB Miss handlers
26 * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
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/linux-5.10/Documentation/core-api/
Dcachetlb.rst2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
44 the TLB. After running, this interface must make sure that
47 there will be no entries in the TLB for 'mm'.
57 address translations from the TLB. After running, this
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/linux-5.10/include/asm-generic/
Dtlb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* include/asm-generic/tlb.h
4 * Generic TLB shootdown code
32 * Generic MMU-gather implementation.
35 * correct and efficient ordering of freeing pages and TLB invalidations.
40 * 2) TLB invalidate page
49 * - tlb_gather_mmu() / tlb_finish_mmu(); start and finish a mmu_gather
51 * Finish in particular will issue a (final) TLB invalidate and free
54 * - tlb_start_vma() / tlb_end_vma(); marks the start / end of a VMA
59 * - tlb_remove_table()
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/linux-5.10/arch/parisc/include/uapi/asm/
Dpdc.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 #define PDC_BAD_PROC -1 /* Called non-existent procedure*/
15 #define PDC_BAD_OPTION -2 /* Called with non-existent option */
16 #define PDC_ERROR -3 /* Call could not complete without an error */
17 #define PDC_NE_MOD -5 /* Module not found */
18 #define PDC_NE_CELL_MOD -7 /* Cell module not found */
19 #define PDC_NE_BOOTDEV -9 /* Cannot locate a console device or boot device */
20 #define PDC_INVALID_ARG -10 /* Called with an invalid argument */
21 #define PDC_BUS_POW_WARN -12 /* Call could not complete in allowed power budget */
22 #define PDC_NOT_NARROW -17 /* Narrow mode not supported */
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/linux-5.10/drivers/parisc/
Dccio-dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 ** ccio-dma.c:
4 ** DMA management routines for first generation cache-coherent machines.
9 ** (c) Copyright 2000 Hewlett-Packard Company
15 ** the I/O MMU - basically what x86 does.
17 ** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at:
18 ** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc
19 ** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c
21 ** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c.
24 ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).
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/linux-5.10/arch/sparc/kernel/
Dtsb.S1 /* SPDX-License-Identifier: GPL-2.0 */
17 /* Invoked from TLB miss handler, we are in the
23 * %g3: FAULT_CODE_{D,I}TLB
46 * %g1 -- PAGE_SIZE TSB entry address
47 * %g3 -- FAULT_CODE_{D,I}TLB
48 * %g4 -- missing virtual address
49 * %g6 -- TAG TARGET (vaddr >> 22)
67 cmp %g5, -1
106 * %g1 -- TSB entry address
107 * %g3 -- FAULT_CODE_{D,I}TLB
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Dktlb.S1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* arch/sparc64/kernel/ktlb.S: Kernel mapping TLB miss handling.
57 /* fallthrough to TLB load */
70 * instruction get nop'd out and we get here to branch
71 * to the sun4v tlb load code. The registers are setup
78 * The sun4v TLB load wants the PTE in %g3 so we fix that
148 /* Index through the base page size TSB even for linear
169 /* fallthrough to TLB load */
173 661: stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
182 * instruction get nop'd out and we get here to branch
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/linux-5.10/arch/powerpc/mm/nohash/
D44x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * -- paulus
11 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
27 #include <asm/code-patching.h>
31 /* Used by the 44x TLB replacement exception handler.
35 unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
42 /* The TLB miss handlers hard codes the watermark in a cmpli in ppc44x_update_tlb_hwater()
45 * in the 2 TLB miss handlers when updating the value in ppc44x_update_tlb_hwater()
52 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 44x type MMU
56 unsigned int entry = tlb_44x_hwater--; in ppc44x_pin_tlb()
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/linux-5.10/arch/arc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
98 source "arch/arc/plat-tb10x/Kconfig"
99 source "arch/arc/plat-axs10x/Kconfig"
100 source "arch/arc/plat-hsdk/Kconfig"
118 ISA for the Next Generation ARC-HS cores
143 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
144 Shared Address Spaces (for sharing TLB entries in MMU)
145 -Caches: New Prog Model, Region Flush
146 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
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/linux-5.10/arch/ia64/include/asm/
Dmmu_context.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 1998-2002 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * numbers are used to reduce or eliminate the need to perform TLB flushes
13 * due to context switches. Context numbers are implemented using ia-64
14 * region ids. Since the IA-64 TLB does not consider the region number when
15 * performing a TLB lookup, we need to assign a unique region id to each
20 #define IA64_REGION_ID_KERNEL 0 /* the kernel's region id (tlb.c depends on this being 0) */
34 #include <asm-generic/mm_hooks.h>
42 unsigned long *bitmap; /* bitmap size is max_ctx+1 */
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/linux-5.10/tools/perf/pmu-events/arch/powerpc/power9/
Dpipeline.json10 "BriefDescription": "Number of I-ERAT reloads"
25 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued…
35 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ…
40 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl…
80 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
95 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
110 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K"
115 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispa…
120 …"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) and 1G (radi…
160 …"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data fro…
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Dother.json50 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
65 "BriefDescription": "Read-write data cache collisions"
75 … "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) or 1G (radix mode)"
85 …"BriefDescription": "A radix translation attempt missed in the TLB and all levels of page walk cac…
90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core"
200 "BriefDescription": "Read-write data cache collisions"
280 …-word boundary, which causes it to require an additional slice than than what normally would be re…
300 "BriefDescription": "I-cache Invalidates sent over the realod bus to the core"
395 …-word boundary, which causes it to require an additional slice than than what normally would be re…
430 "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)"
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/linux-5.10/arch/arc/include/asm/
Dpgtable.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -Folded PAGE_PRESENT (used by VM) and PAGE_VALID (used by MMU) into 1.
8 * VALID marks a TLB entry exists and it will only happen if PRESENT
9 * - Utilise some unused free bits to confine PTE flags to 12 bits
10 * This is a must for 4k pg-sz
12 * vineetg: Mar 2011 - changes to accommodate MMU TLB Page Descriptor mods
13 * -TLB Locking never really existed, except for initial specs
14 * -SILENT_xxx not needed for our port
15 * -Per my request, MMU V3 changes the layout of some of the bits
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/linux-5.10/drivers/firmware/efi/
Dcper-arm.c1 // SPDX-License-Identifier: GPL-2.0
71 …"Local management operation (processor initiated a TLB management operation that resulted in an er…
72 …al management operation (processor raised a TLB error caused by another processor or device broadc…
147 printk("%scache level: %d\n", pfx, level); in cper_print_arm_err_info()
150 printk("%sTLB level: %d\n", pfx, level); in cper_print_arm_err_info()
153 printk("%saffinity level at which the bus error occurred: %d\n", in cper_print_arm_err_info()
246 printk("%sMIDR: 0x%016llx\n", pfx, proc->midr); in cper_print_proc_arm()
248 len = proc->section_length - (sizeof(*proc) + in cper_print_proc_arm()
249 proc->err_info_num * (sizeof(*err_info))); in cper_print_proc_arm()
251 printk("%ssection length: %d\n", pfx, proc->section_length); in cper_print_proc_arm()
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/linux-5.10/arch/arm/mm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
147 instruction sequences for cache and TLB operations. Curiously,
166 Branch Target Buffer, Unified TLB and cache line size 16.
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
190 # ARM946E-S
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/linux-5.10/arch/mips/mm/
Dtlb-r4k.c20 #include <asm/cpu-type.h>
24 #include <asm/tlb.h>
30 * LOONGSON-2 has a 4 entry itlb which is a subset of jtlb, LOONGSON-3 has
50 if (vma->vm_flags & VM_EXEC) in flush_micro_tlb_vm()
109 struct mm_struct *mm = vma->vm_mm; in local_flush_tlb_range()
113 unsigned long size, flags; in local_flush_tlb_range() local
118 size = (end - start) >> (PAGE_SHIFT + 1); in local_flush_tlb_range()
119 if (size <= (current_cpu_data.tlbsizeftlbsets ? in local_flush_tlb_range()
168 unsigned long size, flags; in local_flush_tlb_kernel_range() local
171 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; in local_flush_tlb_kernel_range()
[all …]
Dtlbex.c6 * Synthesize TLB refill handlers at runtime.
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
34 #include <asm/cpu-type.h>
53 * TLB load/store/modify handlers.
132 * CVMSEG starts at address -32768 and extends for in scratchpad_offset()
136 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; in scratchpad_offset()
231 * TLB exception handlers.
242 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); in output_pgtable_bits_defines()
243 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); in output_pgtable_bits_defines()
244 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); in output_pgtable_bits_defines()
[all …]
/linux-5.10/Documentation/arm/
Dinterrupts.rst5 2.5.2-rmk5:
7 major architecture-specific subsystems.
10 MMU TLB. Each MMU TLB variant is now handled completely separately -
11 we have TLB v3, TLB v4 (without write buffer), TLB v4 (with write buffer),
12 and finally TLB v4 (with write buffer, with I TLB invalidate entry).
14 allow more flexible TLB handling for the future.
26 SA1100 ------------> Neponset -----------> SA1111
28 -----------> USAR
30 -----------> SMC9196
33 exclusive of each other - if you're processing one interrupt from the
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/linux-5.10/arch/sh/include/asm/
Dpgtable_32.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * notes on SH-X2 MMUs and 64-bit PTEs):
11 * - Bits 0 and 7 are reserved on SH-3 (_PAGE_WT and _PAGE_SZ1 on SH-4).
13 * - Bit 1 is the SH-bit, but is unused on SH-3 due to an MMU bug (the
14 * hardware PTEL value can't have the SH-bit set when MMUCR.IX is set,
15 * which is the default in cpu-sh3/mmu_context.h:MMU_CONTROL_INIT).
18 * SH-3 specific flags until all of the other unused bits have been
21 * - Bit 9 is reserved by everyone and used by _PAGE_PROTNONE.
23 * - Bits 10 and 11 are low bits of the PPN that are reserved on >= 4K pages.
26 * - On 29 bit platforms, bits 31 to 29 are used for the space attributes
[all …]
/linux-5.10/arch/ia64/kernel/
Divt.S1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
8 * Copyright (C) 2000, 2002-2003 Intel Co
14 * 00/08/23 Asit Mallick <asit.k.mallick@intel.com> TLB handling for SMP
15 * 00/12/20 David Mosberger-Tang <davidm@hpl.hp.com> DTLB/ITLB handler now uses virtual PT.
17 * Copyright (C) 2005 Hewlett-Packard Co
33 * interruptions like TLB misses.
37 * // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
38 * entry offset ----/ / / / /
39 * entry number ---------/ / / /
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/linux-5.10/arch/sparc/include/asm/
Dtsb.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * power-of-2 sized table of TAG/PTE pairs. The cpu precomputes
11 * TLB miss trap handler software does the actual lookup via something
14 * ldxa [%g0] ASI_{D,I}MMU_TSB_8KB_PTR, %g1
15 * ldxa [%g0] ASI_{D,I}MMU, %g6
20 * bne,pn %xcc, tsb_miss_{d,i}tlb
21 * mov FAULT_CODE_{D,I}TLB, %g3
22 * stxa %g5, [%g0] ASI_{D,I}TLB_DATA_IN
26 * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte
27 * PTE. The TAG is of the same layout as the TLB TAG TARGET mmu
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